Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next

9 files changed, 141 insertions, 141 deletions

diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c
index 29c08c1..dc031c9 100644
--- a/cpu/arm1136/mx31/generic.c
+++ b/cpu/arm1136/mx31/generic.c
@@ -81,12 +81,12 @@ void mx31_gpio_mux(unsigned long mode)
 {
 	unsigned long reg, shift, tmp;
 
-	reg = IOMUXC_BASE + (mode & 0xfc);
+	reg = IOMUXC_BASE + (mode & 0x1fc);
 	shift = (~mode & 0x3) * 8;
 
 	tmp = __REG(reg);
 	tmp &= ~(0xff << shift);
-	tmp |= ((mode >> 8) & 0xff) << shift;
+	tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
 	__REG(reg) = tmp;
 }
 
diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile
index 2be35b2..8ba8ae8 100644
--- a/cpu/mpc512x/Makefile
+++ b/cpu/mpc512x/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o
+COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o iopin.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c
index b59f36d..703e188 100644
--- a/cpu/mpc512x/cpu.c
+++ b/cpu/mpc512x/cpu.c
@@ -131,22 +131,67 @@ void watchdog_reset (void)
 #endif
 
 #ifdef CONFIG_OF_LIBFDT
-void ft_cpu_setup(void *blob, bd_t *bd)
+
+#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
+/*
+ * fdt setup for old device trees
+ * fix up
+ * 	cpu clocks
+ * 	soc clocks
+ * 	ethernet addresses
+ */
+static void old_ft_cpu_setup(void *blob, bd_t *bd)
+{
+	/*
+	 * avoid fixing up by path because that
+	 * produces scary error messages
+	 */
+
+	/*
+	 * old device trees have ethernet nodes with
+	 * device_type = "network"
+	 */
+	do_fixup_by_prop(blob, "device_type", "network", 8,
+		"local-mac-address", bd->bi_enetaddr, 6, 0);
+	do_fixup_by_prop(blob, "device_type", "network", 8,
+		"address", bd->bi_enetaddr, 6, 0);
+	/*
+	 * old device trees have soc nodes with
+	 * device_type = "soc"
+	 */
+	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+		"bus-frequency", bd->bi_ipsfreq, 0);
+}
+#endif
+
+static void ft_clock_setup(void *blob, bd_t *bd)
 {
 	char *cpu_path = "/cpus/" OF_CPU;
-	char *eth_path = "/" OF_SOC "/ethernet@2800";
-	char *eth_path_old = "/" OF_SOC_OLD "/ethernet@2800";
-
-	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
-	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
-	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
-	do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipsfreq, 1);
-	do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
-
-	/* this is so old kernels with old device trees will boot */
-	do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0);
-	do_fixup_by_path(blob, eth_path_old, "local-mac-address",
-			bd->bi_enetaddr, 6, 0);
-	do_fixup_by_path(blob, eth_path_old, "address", bd->bi_enetaddr, 6, 0);
+
+	/*
+	 * fixup cpu clocks using path
+	 */
+	do_fixup_by_path_u32(blob, cpu_path,
+		"timebase-frequency", OF_TBCLK, 1);
+	do_fixup_by_path_u32(blob, cpu_path,
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_path_u32(blob, cpu_path,
+		"clock-frequency", bd->bi_intfreq, 1);
+	/*
+	 * fixup soc clocks using compatible
+	 */
+	do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
+		"bus-frequency", bd->bi_ipsfreq, 1);
+}
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
+	old_ft_cpu_setup(blob, bd);
+#endif
+	ft_clock_setup(blob, bd);
+#ifdef CONFIG_HAS_ETH0
+	fdt_fixup_ethernet(blob, bd);
+#endif
 }
 #endif
diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c
new file mode 100644
index 0000000..3d7042d
--- /dev/null
+++ b/cpu/mpc512x/iopin.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2008
+ * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
+ * mpc512x I/O pin/pad initialization for the ADS5121 board
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <mpc512x.h>
+
+void iopin_initialize(iopin_t *ioregs_init, int len)
+{
+	short i, j, p;
+	u_long *reg;
+	immap_t *im = (immap_t *)CFG_IMMR;
+
+	reg = (u_long *)&(im->io_ctrl.regs[0]);
+
+	if (sizeof(ioregs_init) == 0)
+		return;
+
+	for (i = 0; i < len; i++) {
+		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
+			p < ioregs_init[i].nr_pins; p++, j++) {
+			if (ioregs_init[i].bit_or)
+				reg[j] |= ioregs_init[i].val;
+			else
+				reg[j] = ioregs_init[i].val;
+		}
+	}
+	return;
+}
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index 940f5c0..8230364 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -457,7 +457,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
 void ft_pci_setup(void *blob, bd_t *bd)
 {
 	do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
-		"clock-frequency", bd->pci_clk, 1);
+		"clock-frequency", gd->pci_clk, 1);
 }
 #endif
 
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 554830f..4e09c9c 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -147,7 +147,7 @@ static void pq3_mp_up(unsigned long bootpg)
 	out_be32(&gur->devdisr, devdisr);
 
 	/* release the hounds */
-	up = ((1 << CONFIG_NR_CPUS) - 1);
+	up = ((1 << CONFIG_NUM_CPUS) - 1);
 	bpcr = in_be32(&ecm->eebpcr);
 	bpcr |= (up << 24);
 	out_be32(&ecm->eebpcr, bpcr);
@@ -157,7 +157,7 @@ static void pq3_mp_up(unsigned long bootpg)
 	/* wait for everyone */
 	while (timeout) {
 		int i;
-		for (i = 0; i < CONFIG_NR_CPUS; i++) {
+		for (i = 0; i < CONFIG_NUM_CPUS; i++) {
 			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
 				cpu_up_mask |= (1 << i);
 		};
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index a47edae..75676b5 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -173,7 +173,7 @@ __secondary_start_page:
 	.align L1_CACHE_SHIFT
 	.globl __spin_table
 __spin_table:
-	.space CONFIG_NR_CPUS*ENTRY_SIZE
+	.space CONFIG_NUM_CPUS*ENTRY_SIZE
 
 	/* Fill in the empty space.  The actual reset vector is
 	 * the last word of the page */
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 78ba1ea..1fda3fe 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -26,8 +26,10 @@
  * cpu_init.c - low level cpu init
  */
 
+#include <config.h>
 #include <common.h>
 #include <mpc86xx.h>
+#include <asm/mmu.h>
 #include <asm/fsl_law.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -121,3 +123,26 @@ int cpu_init_r(void)
 {
 	return 0;
 }
+
+/* Set up BAT registers */
+void setup_bats(void)
+{
+	write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L);
+	write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L);
+	write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L);
+	write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L);
+	write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L);
+	write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L);
+	write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L);
+	write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L);
+	write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L);
+	write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L);
+	write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L);
+	write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L);
+	write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L);
+	write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L);
+	write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L);
+	write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L);
+
+	return;
+}
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index c39dc46..03f2128 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -358,125 +358,6 @@ invalidate_bats:
 	sync
 	blr
 
-
-	/* setup_bats - set them up to some initial state */
-	/* Skip any BATS setup in early_bats */
-	.globl	setup_bats
-setup_bats:
-
-	addis	r0, r0, 0x0000
-
-	/* IBAT 0 */
-	addis	r4, r0, CFG_IBAT0L@h
-	ori	r4, r4, CFG_IBAT0L@l
-	addis	r3, r0, CFG_IBAT0U@h
-	ori	r3, r3, CFG_IBAT0U@l
-	mtspr	IBAT0L, r4
-	mtspr	IBAT0U, r3
-	isync
-
-	/* DBAT 0 */
-	addis	r4, r0, CFG_DBAT0L@h
-	ori	r4, r4, CFG_DBAT0L@l
-	addis	r3, r0, CFG_DBAT0U@h
-	ori	r3, r3, CFG_DBAT0U@l
-	mtspr	DBAT0L, r4
-	mtspr	DBAT0U, r3
-	isync
-
-	/* IBAT 1 */
-	addis	r4, r0, CFG_IBAT1L@h
-	ori	r4, r4, CFG_IBAT1L@l
-	addis	r3, r0, CFG_IBAT1U@h
-	ori	r3, r3, CFG_IBAT1U@l
-	mtspr	IBAT1L, r4
-	mtspr	IBAT1U, r3
-	isync
-
-	/* DBAT 1 */
-	addis	r4, r0, CFG_DBAT1L@h
-	ori	r4, r4, CFG_DBAT1L@l
-	addis	r3, r0, CFG_DBAT1U@h
-	ori	r3, r3, CFG_DBAT1U@l
-	mtspr	DBAT1L, r4
-	mtspr	DBAT1U, r3
-	isync
-
-	/* IBAT 2 */
-	addis	r4, r0, CFG_IBAT2L@h
-	ori	r4, r4, CFG_IBAT2L@l
-	addis	r3, r0, CFG_IBAT2U@h
-	ori	r3, r3, CFG_IBAT2U@l
-	mtspr	IBAT2L, r4
-	mtspr	IBAT2U, r3
-	isync
-
-	/* DBAT 2 */
-	addis	r4, r0, CFG_DBAT2L@h
-	ori	r4, r4, CFG_DBAT2L@l
-	addis	r3, r0, CFG_DBAT2U@h
-	ori	r3, r3, CFG_DBAT2U@l
-	mtspr	DBAT2L, r4
-	mtspr	DBAT2U, r3
-	isync
-
-	/* IBAT 3 */
-	addis	r4, r0, CFG_IBAT3L@h
-	ori	r4, r4, CFG_IBAT3L@l
-	addis	r3, r0, CFG_IBAT3U@h
-	ori	r3, r3, CFG_IBAT3U@l
-	mtspr	IBAT3L, r4
-	mtspr	IBAT3U, r3
-	isync
-
-	/* DBAT 3 */
-	addis	r4, r0, CFG_DBAT3L@h
-	ori	r4, r4, CFG_DBAT3L@l
-	addis	r3, r0, CFG_DBAT3U@h
-	ori	r3, r3, CFG_DBAT3U@l
-	mtspr	DBAT3L, r4
-	mtspr	DBAT3U, r3
-	isync
-
-	/* IBAT 4 */
-	addis	r4, r0, CFG_IBAT4L@h
-	ori	r4, r4, CFG_IBAT4L@l
-	addis	r3, r0, CFG_IBAT4U@h
-	ori	r3, r3, CFG_IBAT4U@l
-	mtspr	IBAT4L, r4
-	mtspr	IBAT4U, r3
-	isync
-
-	/* DBAT 4 */
-	addis	r4, r0, CFG_DBAT4L@h
-	ori	r4, r4, CFG_DBAT4L@l
-	addis	r3, r0, CFG_DBAT4U@h
-	ori	r3, r3, CFG_DBAT4U@l
-	mtspr	DBAT4L, r4
-	mtspr	DBAT4U, r3
-	isync
-
-	/* IBAT 7 */
-	addis	r4, r0, CFG_IBAT7L@h
-	ori	r4, r4, CFG_IBAT7L@l
-	addis	r3, r0, CFG_IBAT7U@h
-	ori	r3, r3, CFG_IBAT7U@l
-	mtspr	IBAT7L, r4
-	mtspr	IBAT7U, r3
-	isync
-
-	/* DBAT 7 */
-	addis	r4, r0, CFG_DBAT7L@h
-	ori	r4, r4, CFG_DBAT7L@l
-	addis	r3, r0, CFG_DBAT7U@h
-	ori	r3, r3, CFG_DBAT7U@l
-	mtspr	DBAT7L, r4
-	mtspr	DBAT7U, r3
-	isync
-
-	sync
-	blr
-
 /*
  * early_bats:
  *