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| author | Andy Fleming <afleming@freescale.com> | 2007-04-23 01:44:44 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-04-23 19:58:28 -0500 |
| commit | 03b81b48eec0ad249ec97a4ae16c36fa2e014ff4 (patch) | |
| tree | 03b43915fd165ad080a5c9ca7eef21f94e38e9fd /cpu | |
| parent | 151d5d992eab8c497b24c816c73dc1ad8bffb4eb (diff) | |
| download | u-boot-imx-03b81b48eec0ad249ec97a4ae16c36fa2e014ff4.zip u-boot-imx-03b81b48eec0ad249ec97a4ae16c36fa2e014ff4.tar.gz u-boot-imx-03b81b48eec0ad249ec97a4ae16c36fa2e014ff4.tar.bz2 | |
Some 85xx cpu cleanups
* Cleaned up the TSR[WIS] clearing
* Cleaned up DMA initialization
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 2fe6bdf..b701b47 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -198,9 +198,9 @@ reset_85xx_watchdog(void) * Clear TSR(WIS) bit by writing 1 */ unsigned long val; - val = mfspr(tsr); - val |= 0x40000000; - mtspr(tsr, val); + val = mfspr(SPRN_TSR); + val |= TSR_WIS; + mtspr(SPRN_TSR, val); } #endif /* CONFIG_WATCHDOG */ @@ -211,6 +211,7 @@ void dma_init(void) { dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; + dma->sr0 = 0xfffffff; /* clear any errors */ asm("sync; isync; msync"); return; } @@ -225,6 +226,10 @@ uint dma_check(void) { status = dma->sr0; } + /* clear MR0[CS] channel start bit */ + dma->mr0 &= 0x00000001; + asm("sync;isync;msync"); + if (status != 0) { printf ("DMA Error: status = %x\n", status); } |