[Microblaze][PATCH]

timer support
interrupt controller support
flash support
ethernet support
cache support
board information support
env support
booting image support

adding support for Xilinx ML401

8 files changed, 570 insertions, 0 deletions

diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
new file mode 100644
index 0000000..fc388eb
--- /dev/null
+++ b/cpu/microblaze/cache.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <moonstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
+
+int dcache_status (void)
+{
+	int i = 0;
+	int mask = 0x80;
+	__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
+	/* i&=0x80 */
+	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
+	return i;
+}
+
+int icache_status (void)
+{
+	int i = 0;
+	int mask = 0x20;
+	__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
+	/* i&=0x20 */
+	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
+	return i;
+}
+#endif
diff --git a/cpu/microblaze/dcache.S b/cpu/microblaze/dcache.S
new file mode 100644
index 0000000..eaf9671
--- /dev/null
+++ b/cpu/microblaze/dcache.S
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+	.text
+	.globl	dcache_enable
+	.ent	dcache_enable
+	.align	2
+dcache_enable:
+	/* Make space on stack for a temporary */
+	addi	r1, r1, -4
+	/* Save register r12 */
+	swi	r12, r1, 0
+	/* Read the MSR register */
+	mfs	r12, rmsr
+	/* Set the instruction enable bit */
+	ori	r12, r12, 0x80
+	/* Save the MSR register */
+	mts	rmsr, r12
+	/* Load register r12 */
+	lwi	r12, r1, 0
+	/* Return */
+	rtsd	r15, 8
+	/* Update stack in the delay slot */
+	addi	r1, r1, 4
+	.end	dcache_enable
+
+	.text
+	.globl	dcache_disable
+	.ent	dcache_disable
+	.align	2
+dcache_disable:
+	/* Make space on stack for a temporary */
+	addi	r1, r1, -4
+	/* Save register r12 */
+	swi	r12, r1, 0
+	/* Read the MSR register */
+	mfs	r12, rmsr
+	/* Clear the data cache enable bit */
+	andi	r12, r12, ~0x80
+	/* Save the MSR register */
+	mts	rmsr, r12
+	/* Load register r12 */
+	lwi	r12, r1, 0
+	/* Return */
+	rtsd	r15, 8
+	/* Update stack in the delay slot */
+	addi	r1, r1, 4
+	.end	dcache_disable
diff --git a/cpu/microblaze/disable_int.S b/cpu/microblaze/disable_int.S
new file mode 100644
index 0000000..aecd795
--- /dev/null
+++ b/cpu/microblaze/disable_int.S
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+	.text
+	.globl	microblaze_disable_interrupts
+	.ent	microblaze_disable_interrupts
+	.align	2
+microblaze_disable_interrupts:
+	#Make space on stack for a temporary
+	addi	r1, r1, -4
+	#Save register r12
+	swi	r12, r1, 0
+	#Read the MSR register
+	mfs	r12, rmsr
+	#Clear the interrupt enable bit
+	andi	r12, r12, ~2
+	#Save the MSR register
+	mts	rmsr, r12
+	#Load register r12
+	lwi	r12, r1, 0
+	#Return
+	rtsd	r15, 8
+	#Update stack in the delay slot
+	addi	r1, r1, 4
+	.end	microblaze_disable_interrupts
diff --git a/cpu/microblaze/enable_int.S b/cpu/microblaze/enable_int.S
new file mode 100644
index 0000000..c096c6c
--- /dev/null
+++ b/cpu/microblaze/enable_int.S
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstrmonstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+	.text
+	.globl	microblaze_enable_interrupts
+	.ent	microblaze_enable_interrupts
+	.align	2
+microblaze_enable_interrupts:
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	mfs	r12, rmsr
+	ori	r12, r12, 2
+	mts	rmsr, r12
+	lwi	r12, r1, 0
+	rtsd	r15, 8
+	addi	r1, r1, 4
+	.end	microblaze_enable_interrupts
diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c
new file mode 100644
index 0000000..b135acb
--- /dev/null
+++ b/cpu/microblaze/exception.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void _hw_exception_handler (void)
+{
+	int address = 0;
+	int state = 0;
+	/* loading address of exception EAR */
+	__asm__ __volatile ("mfs %0,rear"::"r" (address):"memory");
+	/* loading excetpion state register ESR */
+	__asm__ __volatile ("mfs %0,resr"::"r" (state):"memory");
+	printf ("Hardware exception at 0x%x address\n", address);
+	switch (state & 0x1f) {	/* mask on exception cause */
+	case 0x1:
+		puts ("Unaligned data access exception\n");
+		break;
+	case 0x2:
+		puts ("Illegal op-code exception\n");
+		break;
+	case 0x3:
+		puts ("Instruction bus error exception\n");
+		break;
+	case 0x4:
+		puts ("Data bus error exception\n");
+		break;
+	case 0x5:
+		puts ("Divide by zero exception\n");
+		break;
+	default:
+		puts ("Undefined cause\n");
+		break;
+	}
+	printf ("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
+	printf ("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
+	printf ("Register R%x\n", (state & 0x3E) >> 5);
+	hang ();
+}
+
+#ifdef CFG_USR_EXCEP
+void _exception_handler (void)
+{
+	puts ("User vector_exception\n");
+	hang ();
+}
+#endif
diff --git a/cpu/microblaze/icache.S b/cpu/microblaze/icache.S
new file mode 100644
index 0000000..25940d1
--- /dev/null
+++ b/cpu/microblaze/icache.S
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+	.text
+	.globl	icache_enable
+	.ent	icache_enable
+	.align	2
+icache_enable:
+	/* Make space on stack for a temporary */
+	addi	r1, r1, -4
+	/* Save register r12 */
+	swi	r12, r1, 0
+	/* Read the MSR register */
+	mfs	r12, rmsr
+	/* Set the instruction enable bit */
+	ori	r12, r12, 0x20
+	/* Save the MSR register */
+	mts	rmsr, r12
+	/* Load register r12 */
+	lwi	r12, r1, 0
+	/* Return */
+	rtsd	r15, 8
+	/* Update stack in the delay slot */
+	addi	r1, r1, 4
+	.end	icache_enable
+
+	.text
+	.globl	icache_disable
+	.ent	icache_disable
+	.align	2
+icache_disable:
+	/* Make space on stack for a temporary */
+	addi	r1, r1, -4
+	/* Save register r12 */
+	swi	r12, r1, 0
+	/* Read the MSR register */
+	mfs	r12, rmsr
+	/* Clear the instruction enable bit */
+	andi	r12, r12, ~0x20
+	/* Save the MSR register */
+	mts	rmsr, r12
+	/* Load register r12 */
+	lwi	r12, r1, 0
+	/* Return */
+	rtsd	r15, 8
+	/* Update stack in the delay slot */
+	addi	r1, r1, 4
+	.end	icache_disable
diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S
new file mode 100644
index 0000000..a4e3fbf
--- /dev/null
+++ b/cpu/microblaze/irq.S
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+	.text
+	.global _interrupt_handler
+_interrupt_handler:
+	addi	r1, r1, -4
+	swi	r2, r1, 0
+	addi	r1, r1, -4
+	swi	r3, r1, 0
+	addi	r1, r1, -4
+	swi	r4, r1, 0
+	addi	r1, r1, -4
+	swi	r5, r1, 0
+	addi	r1, r1, -4
+	swi	r6, r1, 0
+	addi	r1, r1, -4
+	swi	r7, r1, 0
+	addi	r1, r1, -4
+	swi	r8, r1, 0
+	addi	r1, r1, -4
+	swi	r9, r1, 0
+	addi	r1, r1, -4
+	swi	r10, r1, 0
+	addi	r1, r1, -4
+	swi	r11, r1, 0
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	addi	r1, r1, -4
+	swi	r13, r1, 0
+	addi	r1, r1, -4
+	swi	r14, r1, 0
+	addi	r1, r1, -4
+	swi	r15, r1, 0
+	addi	r1, r1, -4
+	swi	r16, r1, 0
+	addi	r1, r1, -4
+	swi	r17, r1, 0
+	addi	r1, r1, -4
+	swi	r18, r1, 0
+	addi	r1, r1, -4
+	swi	r19, r1, 0
+	addi	r1, r1, -4
+	swi	r20, r1, 0
+	addi	r1, r1, -4
+	swi	r21, r1, 0
+	addi	r1, r1, -4
+	swi	r22, r1, 0
+	addi	r1, r1, -4
+	swi	r23, r1, 0
+	addi	r1, r1, -4
+	swi	r24, r1, 0
+	addi	r1, r1, -4
+	swi	r25, r1, 0
+	addi	r1, r1, -4
+	swi	r26, r1, 0
+	addi	r1, r1, -4
+	swi	r27, r1, 0
+	addi	r1, r1, -4
+	swi	r28, r1, 0
+	addi	r1, r1, -4
+	swi	r29, r1, 0
+	addi	r1, r1, -4
+	swi	r30, r1, 0
+	addi	r1, r1, -4
+	swi	r31, r1, 0
+	brlid	r15, interrupt_handler
+	nop
+	nop
+	lwi	r31, r1, 0
+	addi	r1, r1, 4
+	lwi	r30, r1, 0
+	addi	r1, r1, 4
+	lwi	r29, r1, 0
+	addi	r1, r1, 4
+	lwi	r28, r1, 0
+	addi	r1, r1, 4
+	lwi	r27, r1, 0
+	addi	r1, r1, 4
+	lwi	r26, r1, 0
+	addi	r1, r1, 4
+	lwi	r25, r1, 0
+	addi	r1, r1, 4
+	lwi	r24, r1, 0
+	addi	r1, r1, 4
+	lwi	r23, r1, 0
+	addi	r1, r1, 4
+	lwi	r22, r1, 0
+	addi	r1, r1, 4
+	lwi	r21, r1, 0
+	addi	r1, r1, 4
+	lwi	r20, r1, 0
+	addi	r1, r1, 4
+	lwi	r19, r1, 0
+	addi	r1, r1, 4
+	lwi	r18, r1, 0
+	addi	r1, r1, 4
+	lwi	r17, r1, 0
+	addi	r1, r1, 4
+	lwi	r16, r1, 0
+	addi	r1, r1, 4
+	lwi	r15, r1, 0
+	addi	r1, r1, 4
+	lwi	r14, r1, 0
+	addi	r1, r1, 4
+	lwi	r13, r1, 0
+	addi	r1, r1, 4
+	lwi	r12, r1, 0
+	addi	r1, r1, 4
+	lwi	r11, r1, 0
+	addi	r1, r1, 4
+	lwi	r10, r1, 0
+	addi	r1, r1, 4
+	lwi	r9, r1, 0
+	addi	r1, r1, 4
+	lwi	r8, r1, 0
+	addi	r1, r1, 4
+	lwi	r7, r1, 0
+	addi	r1, r1, 4
+	lwi	r6, r1, 0
+	addi	r1, r1, 4
+	lwi	r5, r1, 0
+	addi	r1, r1, 4
+	lwi	r4, r1, 0
+	addi	r1, r1, 4
+	lwi	r3, r1, 0
+	addi	r1, r1, 4
+	lwi	r2, r1, 0
+	addi	r1, r1, 4
+
+	/* enable_interrupt */
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	mfs	r12, rmsr
+	ori	r12, r12, 2
+	mts	rmsr, r12
+	lwi	r12, r1, 0
+	addi	r1, r1, 4
+	nop
+	bra	r14
+	nop
+	nop
+	.size _interrupt_handler,.-_interrupt_handler
diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c
new file mode 100644
index 0000000..be4fd57
--- /dev/null
+++ b/cpu/microblaze/timer.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/microblaze_timer.h>
+
+volatile int timestamp = 0;
+
+void reset_timer (void)
+{
+	timestamp = 0;
+}
+
+ulong get_timer (ulong base)
+{
+	return (timestamp - base);
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+#ifdef CFG_INTC_0
+#ifdef CFG_TIMER_0
+extern void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+				       void *arg);
+
+microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR);
+
+void timer_isr (void *arg)
+{
+	timestamp++;
+	tmr->control = tmr->control | TIMER_INTERRUPT;
+}
+
+void timer_init (void)
+{
+	tmr->loadreg = CFG_TIMER_0_PRELOAD;
+	tmr->control = TIMER_INTERRUPT | TIMER_RESET;
+	tmr->control =
+	    TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
+	reset_timer ();
+	install_interrupt_handler (CFG_TIMER_0_IRQ, timer_isr, (void *)tmr);
+}
+#endif
+#endif