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| author | Wolfgang Denk <wd@denx.de> | 2007-11-02 15:09:10 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-11-02 15:09:10 +0100 |
| commit | f0516920f6e048425b005c049378e80d600bd268 (patch) | |
| tree | 8038bb6bc203daf2ad4a9aa4d2e246f10f12a7c1 /cpu | |
| parent | 5b746c3ea8c72035621435853d5b5278af0a1011 (diff) | |
| parent | 8b6684a698500be9c142ec2c9f46cfc348e17f0c (diff) | |
| download | u-boot-imx-f0516920f6e048425b005c049378e80d600bd268.zip u-boot-imx-f0516920f6e048425b005c049378e80d600bd268.tar.gz u-boot-imx-f0516920f6e048425b005c049378e80d600bd268.tar.bz2 | |
Merge branch 'master' of /home/wd/git/u-boot/custodians
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mcf52x2/start.S | 6 | ||||
| -rw-r--r-- | cpu/mcf532x/start.S | 4 |
2 files changed, 7 insertions, 3 deletions
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 686e2a5..260a09a 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -58,7 +58,7 @@ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ #if defined(CONFIG_R5200) .long 0x400 -#elif defined(CONFIG_M5282) +#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) .long _start - TEXT_BASE #else .long _START @@ -177,7 +177,11 @@ _after_flashbar_copy: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) +#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) + move.l #CFG_INT_FLASH_BASE, %d0 +#else move.l #CFG_FLASH_BASE, %d0 +#endif movec %d0, %VBR #endif diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index 5cc1c87..61be2ea 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -131,7 +131,7 @@ _start: movec %d0, %VBR move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR0 + movec %d0, %RAMBAR1 /* invalidate and disable cache */ move.l #0x01000000, %d0 /* Invalidate cache cmd */ @@ -268,7 +268,7 @@ _int_handler: icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ - move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0 + move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 movec %d0, %ACR0 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ |