diff options
| author | Wolfgang Denk <wd@denx.de> | 2008-08-23 00:10:43 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-08-23 00:10:43 +0200 |
| commit | afe3848b79a7ff351e9fbf3a7c162d2de002279b (patch) | |
| tree | fdf882941bd33990975fa638fbf11486b1894c54 /cpu | |
| parent | 0bb86d823b6c150c7ee17de0cfca9ffccc16463b (diff) | |
| parent | 5d4b3d2b31e58fcb2d4bd10af762f5ff41b229fd (diff) | |
| download | u-boot-imx-afe3848b79a7ff351e9fbf3a7c162d2de002279b.zip u-boot-imx-afe3848b79a7ff351e9fbf3a7c162d2de002279b.tar.gz u-boot-imx-afe3848b79a7ff351e9fbf3a7c162d2de002279b.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 17 | ||||
| -rw-r--r-- | cpu/ppc4xx/4xx_pcie.c | 10 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu_init.c | 13 |
3 files changed, 31 insertions, 9 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 1c36324..001f2c1 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -2249,17 +2249,26 @@ static void program_memory_queue(unsigned long *dimm_populated, } } -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) /* - * Enable high bandwidth access on 460EX/GT. - * This should/could probably be done on other - * PPC's too, like 440SPe. + * Enable high bandwidth access * This is currently not used, but with this setup * it is possible to use it later on in e.g. the Linux * EMAC driver for performance gain. */ mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */ mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */ + + /* + * Set optimal value for Memory Queue HB/LL Configuration registers + */ + mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | + SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE); + mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | + SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE); + mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); #endif } diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 9803fcc..0aadc06 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -638,7 +638,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) switch (port) { case 0: SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230); - SDR_WRITE(PESDR0_L0DRV, 0x00000136); + SDR_WRITE(PESDR0_L0DRV, 0x00000130); SDR_WRITE(PESDR0_L0CLK, 0x00000006); SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000); @@ -649,10 +649,10 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport) SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230); SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230); SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230); - SDR_WRITE(PESDR1_L0DRV, 0x00000136); - SDR_WRITE(PESDR1_L1DRV, 0x00000136); - SDR_WRITE(PESDR1_L2DRV, 0x00000136); - SDR_WRITE(PESDR1_L3DRV, 0x00000136); + SDR_WRITE(PESDR1_L0DRV, 0x00000130); + SDR_WRITE(PESDR1_L1DRV, 0x00000130); + SDR_WRITE(PESDR1_L2DRV, 0x00000130); + SDR_WRITE(PESDR1_L3DRV, 0x00000130); SDR_WRITE(PESDR1_L0CLK, 0x00000006); SDR_WRITE(PESDR1_L1CLK, 0x00000006); SDR_WRITE(PESDR1_L2CLK, 0x00000006); diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index e2d0402..dee9807 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -301,6 +301,19 @@ cpu_init_f (void) val |= 0x400; mtsdr(SDR0_USB2HOST_CFG, val); #endif /* CONFIG_460EX */ + +#if defined(CONFIG_405EX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + /* + * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read + */ + mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | + plb0_acr_rdp_4deep); + mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | + plb1_acr_rdp_4deep); +#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ } /* |