ENGR00121379: MX28 U-BOOT enhancements

MX28 U-BOOT enhancements.

Signed-off-by: Terry Lv <r65388@freescale.com>

6 files changed, 106 insertions, 336 deletions

diff --git a/cpu/arm926ejs/mx28/generic.c b/cpu/arm926ejs/mx28/generic.c
index 6ac75e0..82929d5 100644
--- a/cpu/arm926ejs/mx28/generic.c
+++ b/cpu/arm926ejs/mx28/generic.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,83 +22,120 @@
 
 #include <common.h>
 #include <asm/errno.h>
-#include <asm/arch/mx28.h>
 #include <asm/arch/regs-clkctrl.h>
+#include <asm/cache-cp15.h>
+#include <asm/fec.h>
 
-#if defined(CONFIG_ARCH_CPU_INIT)
-int arch_cpu_init(void)
-{
-	icache_enable();
-	dcache_enable();
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
+static u32 mx28_get_pclk(void)
 {
 	const u32 xtal = 24, ref = 480;
-	u32 cpu, bus, emi;
-	u32 clkfrac, clkdeq, clkctrl;
+	u32 clkfrac, clkseq, clkctrl;
 	u32 frac, div;
+	u32 pclk;
 
 	clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0);
-	clkdeq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ);
-
-	/* CPU */
+	clkseq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ);
 	clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CPU);
+
 	if (clkctrl & (BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN |
 		BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
 		/* No support of fractional divider calculation */
-		cpu = 0;
+		pclk = 0;
 	} else {
-		if (clkdeq & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) {
+		if (clkseq & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) {
 			/* xtal path */
 			div = (clkctrl & BM_CLKCTRL_CPU_DIV_XTAL) >>
 				BP_CLKCTRL_CPU_DIV_XTAL;
-			cpu = xtal / div;
+			pclk = xtal / div;
 		} else {
 			/* ref path */
 			frac = (clkfrac & BM_CLKCTRL_FRAC0_CPUFRAC) >>
 				BP_CLKCTRL_FRAC0_CPUFRAC;
 			div = (clkctrl & BM_CLKCTRL_CPU_DIV_CPU) >>
 				BP_CLKCTRL_CPU_DIV_CPU;
-			cpu =  (ref * 18 / frac) / div;
+			pclk =  (ref * 18 / frac) / div;
 		}
 	}
 
-	/* BUS */
+	return pclk;
+}
+
+static u32 mx28_get_hclk(void)
+{
+	u32 clkctrl, div, hclk;
+
 	clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_HBUS);
+
 	if (clkctrl & BM_CLKCTRL_HBUS_DIV_FRAC_EN) {
 		/* No support of fractional divider calculation */
-		bus = 0;
+		hclk = 0;
 	} else {
 		div = (clkctrl & BM_CLKCTRL_HBUS_DIV) >>
 			BP_CLKCTRL_HBUS_DIV;
-		bus = cpu / div;
+		hclk = mx28_get_pclk() / div;
 	}
 
-	/* EMI */
+	return hclk;
+}
+
+static u32 mx28_get_emiclk(void)
+{
+	const u32 xtal = 24, ref = 480;
+	u32 clkfrac, clkseq, clkctrl;
+	u32 frac, div;
+	u32 emiclk;
+
+	clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0);
+	clkseq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ);
 	clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_EMI);
-	if (clkdeq & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) {
+
+	if (clkseq & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) {
 		/* xtal path */
 		div = (clkctrl & BM_CLKCTRL_EMI_DIV_XTAL) >>
 			BP_CLKCTRL_EMI_DIV_XTAL;
-		emi = xtal / div;
+		emiclk = xtal / div;
 	} else {
 		/* ref path */
 		frac = (clkfrac & BM_CLKCTRL_FRAC0_EMIFRAC) >>
 			BP_CLKCTRL_FRAC0_EMIFRAC;
 		div = (clkctrl & BM_CLKCTRL_EMI_DIV_EMI) >>
 			BP_CLKCTRL_EMI_DIV_EMI;
-		emi =  (ref * 18 / frac) / div;
+		emiclk =  (ref * 18 / frac) / div;
 	}
 
-	/* Print */
+	return emiclk;
+}
+
+u32 mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return mx28_get_pclk() * 1000000;
+	case MXC_AHB_CLK:
+	case MXC_IPG_CLK:
+		return mx28_get_hclk() * 1000000;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_ARCH_CPU_INIT)
+int arch_cpu_init(void)
+{
+	icache_enable();
+	dcache_enable();
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
 	printf("Freescale i.MX28 family\n");
-	printf("CPU:   %d MHz\n", cpu);
-	printf("BUS:   %d MHz\n", bus);
-	printf("EMI:   %d MHz\n", emi);
+	printf("CPU:   %d MHz\n", mx28_get_pclk());
+	printf("BUS:   %d MHz\n", mx28_get_hclk());
+	printf("EMI:   %d MHz\n", mx28_get_emiclk());
 
 	return 0;
 }
@@ -107,13 +144,13 @@ int print_cpuinfo(void)
 /*
  * Initializes on-chip MMC controllers.
  */
-#if defined(CONFIG_MXC_ENET)
+#if defined(CONFIG_IMX_SSP_MMC)
 int imx_ssp_mmc_initialize(bd_t *bis);
 #endif
 int cpu_mmc_init(bd_t *bis)
 {
 	int rc = ENODEV;
-#ifdef CONFIG_IMX_SSP_MMC
+#if defined(CONFIG_IMX_SSP_MMC)
 	rc = imx_ssp_mmc_initialize(bis);
 #endif
 	return rc;
@@ -122,14 +159,29 @@ int cpu_mmc_init(bd_t *bis)
 /*
  * Initializes on-chip ethernet controllers.
  */
-#if defined(CONFIG_MXC_ENET)
-int mxc_enet_initialize(bd_t *bis);
-#endif
 int cpu_eth_init(bd_t *bis)
 {
 	int rc = ENODEV;
-#if defined(CONFIG_MXC_ENET)
-	rc = mxc_enet_initialize(bis);
+#if defined(CONFIG_MXC_FEC)
+	rc = mxc_fec_initialize(bis);
+
+	/* Turn on ENET clocks */
+	REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET,
+		REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET) &
+		~(BM_CLKCTRL_ENET_SLEEP | BM_CLKCTRL_ENET_DISABLE));
+
+	/* Set up ENET PLL for 50 MHz */
+	REG_SET(REGS_CLKCTRL_BASE, HW_CLKCTRL_PLL2CTRL0,
+		BM_CLKCTRL_PLL2CTRL0_POWER);    /* Power on ENET PLL */
+	udelay(10);                             /* Wait 10 us */
+	REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_PLL2CTRL0,
+		BM_CLKCTRL_PLL2CTRL0_CLKGATE);  /* Gate on ENET PLL */
+	REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET,
+		REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET) |
+		BM_CLKCTRL_ENET_CLK_OUT_EN);    /* Enable pad output */
+
+	/* Board level init */
+	enet_board_init();
 #endif
 	return rc;
 }
diff --git a/cpu/arm926ejs/mx28/mmcops.c b/cpu/arm926ejs/mx28/mmcops.c
index eed2046..e1d211b 100644
--- a/cpu/arm926ejs/mx28/mmcops.c
+++ b/cpu/arm926ejs/mx28/mmcops.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -24,7 +24,7 @@
 #include <exports.h>
 #include <mmc.h>
 
-#if defined(CONFIG_GENERIC_MMC) && defined(CONFIG_CUSTOMIZE_MMCOPS)
+#ifdef CONFIG_GENERIC_MMC
 #define MMCOPS_DEBUG
 
 #define MBR_SIGNATURE		0xaa55
@@ -96,7 +96,7 @@ static int mmc_format(int dev)
 
 	/* Warning */
 	printf("WARN: Data on card will get lost with format.\n"
-		"Continue?(y/n)");
+		"Continue? (y/n)");
 	char ch = getc();
 	printf("\n");
 	if (ch != 'y') {
@@ -309,7 +309,7 @@ static int install_sbimage(int dev, void *addr, u32 size)
 	}
 	if (memcmp(addr, addr + sectors * mmc->read_bl_len,
 		sectors * mmc->read_bl_len)) {
-		printf("Verifying sbImage write fails");
+		printf("Verifying sbImage write fails\n");
 		rc = -1;
 		goto out;
 	}
@@ -493,7 +493,7 @@ out:
 	return rc;
 }
 
-int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_mxs_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int dev = 0;
 	struct mmc *mmc;
@@ -501,9 +501,8 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (argc < 2)
 		goto err_out;
 
-	if (strcmp(argv[1], "read") && strcmp(argv[1], "write") &&
-		strcmp(argv[1], "rescan") && strcmp(argv[1], "format") &&
-		strcmp(argv[1], "install") && strcmp(argv[1], "list"))
+	if (strcmp(argv[1], "format") &&
+		strcmp(argv[1], "install"))
 		goto err_out;
 
 	if (argc == 2) { /* list */
@@ -531,26 +530,7 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (argc != 6)
 		goto err_out;
 
-	if (!strcmp(argv[1], "read") || !strcmp(argv[1], "write")) {
-		void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
-		u32 blk = simple_strtoul(argv[4], NULL, 16);
-		u32 cnt = simple_strtoul(argv[5], NULL, 16);
-		u32 n;
-
-		printf("\nMMC %s: dev # %d, block # %d, count %d ... ",
-			argv[1], dev, blk, cnt);
-
-		if (!strcmp(argv[1], "read")) {
-			n = mmc->block_dev.block_read(dev, blk, cnt, addr);
-			/* flush cache after read */
-			flush_cache((ulong)addr, cnt * 512); /* FIXME */
-		} else /* write */
-			n = mmc->block_dev.block_write(dev, blk, cnt, addr);
-
-		printf("%d blocks %s: %s\n", n, argv[1],
-			(n == cnt) ? "OK" : "ERROR");
-		return (n == cnt) ? 0 : -1;
-	} else if (!strcmp(argv[1], "install")) {
+	if (!strcmp(argv[1], "install")) {
 		void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
 		u32 size = simple_strtoul(argv[4], NULL, 16);
 
@@ -568,12 +548,8 @@ err_out:
 }
 
 U_BOOT_CMD(
-	mmc, 6, 1, do_mmcops,
-	"MMC sub system",
-	"mmc read <device num> addr blk# cnt\n"
-	"mmc write <device num> addr blk# cnt\n"
-	"mmc rescan <device num>\n"
-	"mmc format <device num>\n"
-	"mmc install <device num> addr size sbImage/uImage/rootfs\n"
-	"mmc list - lists available devices");
-#endif /* (CONFIG_GENERIC_MMC && CONFIG_CUSTOMIZE_MMCOPS) */
+	mxs_mmc, 6, 1, do_mxs_mmcops,
+	"MXS specific MMC sub system",
+	"mxs_mmc format <device num>\n"
+	"mxs_mmc install <device num> addr size sbImage/uImage/rootfs\n");
+#endif /* CONFIG_GENERIC_MMC */
diff --git a/cpu/arm926ejs/mx28/pinctrl.c b/cpu/arm926ejs/mx28/pinctrl.c
index 88427c8..1bf76b9 100644
--- a/cpu/arm926ejs/mx28/pinctrl.c
+++ b/cpu/arm926ejs/mx28/pinctrl.c
@@ -17,7 +17,6 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <common.h>
-#include <asm/arch/mx28.h>
 #include <asm/arch/regs-pinctrl.h>
 #include <asm/arch/pinctrl.h>
 
diff --git a/cpu/arm926ejs/mx28/serial.c b/cpu/arm926ejs/mx28/serial.c
index 58f7d2a..c39da1b 100644
--- a/cpu/arm926ejs/mx28/serial.c
+++ b/cpu/arm926ejs/mx28/serial.c
@@ -19,7 +19,6 @@
  *
  */
 #include <common.h>
-#include <asm/arch/mx28.h>
 #include <asm/arch/regs-uartdbg.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -38,7 +37,7 @@ void serial_setbrg(void)
 	REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0);
 
 	/* Calculate and set baudrate */
-	quot = (CONFIG_DBGUART_CLK * 4)	/ gd->baudrate;
+	quot = (CONFIG_UARTDBG_CLK * 4)	/ gd->baudrate;
 	REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGFBRD, quot & 0x3f);
 	REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIBRD, quot >> 6);
 
diff --git a/cpu/arm926ejs/mx28/spi.c b/cpu/arm926ejs/mx28/spi.c
deleted file mode 100644
index cad2569..0000000
--- a/cpu/arm926ejs/mx28/spi.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Freescale MX28 SSP/SPI driver
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <asm/arch/spi.h>
-
-#define SPI_NUM_BUSES	2
-#define SPI_NUM_SLAVES	3
-
-/* Initalized in spi_init() depending on SSP port configuration */
-static unsigned long ssp_bases[SPI_NUM_BUSES];
-
-/* Set in spi_set_cfg() depending on which SSP port is being used */
-static unsigned long ssp_base = SSP1_BASE;
-
-/*
- * Init SSP port: SSP1 (@bus = 0) or SSP2 (@bus == 1)
- */
-static void ssp_spi_init(unsigned int bus)
-{
-	u32 spi_div;
-	u32 val = 0;
-
-	if (bus >= SPI_NUM_BUSES) {
-		printf("SPI bus %d doesn't exist\n", bus);
-		return;
-	}
-
-	ssp_base = ssp_bases[bus];
-
-	/* Reset block */
-
-	/* Clear SFTRST */
-	REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
-	while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_SFTRST)
-		;
-
-	/* Clear CLKGATE */
-	REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE);
-
-	/* Set SFTRST and wait until CLKGATE is set */
-	REG_SET(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
-	while (!(REG_RD(ssp_base + SSP_CTRL0) & CTRL0_CLKGATE))
-		;
-
-	/* Clear SFTRST and CLKGATE */
-	REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
-	REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE);
-
-	/*
-	* Set CLK to desired value
-	*/
-
-	spi_div = ((CONFIG_SSP_CLK>>1) + CONFIG_SPI_CLK - 1) / CONFIG_SPI_CLK;
-	val = (2 << TIMING_CLOCK_DIVIDE) | ((spi_div - 1) << TIMING_CLOCK_RATE);
-	REG_WR(ssp_base + SSP_TIMING, val);
-
-	/* Set transfer parameters */
-
-	/* Set SSP SPI Master mode and word length to 8 bit */
-	REG_WR(ssp_base + SSP_CTRL1, WORD_LENGTH8 | SSP_MODE_SPI);
-
-	/* Set BUS_WIDTH to 1 bit and XFER_COUNT to 1 byte */
-	REG_WR(ssp_base + SSP_CTRL0,
-	       BUS_WIDTH_SPI1 | (0x1 << CTRL0_XFER_COUNT));
-
-	/*
-	* Set BLOCK_SIZE and BLOCK_COUNT to 0, so that XFER_COUNT
-	* reflects number of bytes to send. Disalbe other bits as
-	* well
-	*/
-	REG_WR(ssp_base + SSP_CMD0, 0x0);
-}
-
-/*
- * Init SSP ports, must be called first and only once
- */
-void spi_init(void)
-{
-#ifdef CONFIG_SPI_SSP1
-	ssp_bases[0] = SSP1_BASE;
-	ssp_spi_init(0);
-#endif
-
-#ifdef CONFIG_SPI_SSP2
-	ssp_bases[1] = SSP2_BASE;
-	ssp_spi_init(1);
-#endif
-}
-
-void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode)
-{
-	u32 clr_mask = 0;
-	u32 set_mask = 0;
-
-	if (bus >= SPI_NUM_BUSES || cs >= SPI_NUM_SLAVES) {
-		printf("SPI device %d:%d doesn't exist", bus, cs);
-		return;
-	}
-
-	if (ssp_bases[bus] == 0) {
-		printf("SSP port %d isn't in SPI mode\n", bus + 1);
-		return;
-	}
-
-	/* Set SSP port to use */
-	ssp_base = ssp_bases[bus];
-
-	/* Set phase and polarity: HW_SSP_CTRL1 */
-	if (mode & SPI_PHASE)
-		set_mask |= CTRL1_PHASE;
-	else
-		clr_mask |= CTRL1_PHASE;
-
-	if (mode & SPI_POLARITY)
-		set_mask |= CTRL1_POLARITY;
-	else
-		clr_mask |= CTRL1_POLARITY;
-
-	REG_SET(ssp_base + SSP_CTRL1, set_mask);
-	REG_CLR(ssp_base + SSP_CTRL1, clr_mask);
-
-	/* Set SSn number: HW_SSP_CTRL0 */
-	REG_CLR(ssp_base + SSP_CTRL0, SPI_CS_CLR_MASK);
-
-	switch (cs) {
-	case 0:
-		set_mask = SPI_CS0;
-		break;
-	case 1:
-		set_mask = SPI_CS1;
-		break;
-	case 2:
-		set_mask = SPI_CS2;
-		break;
-	}
-
-	REG_SET(ssp_base + SSP_CTRL0, set_mask);
-}
-
-/* Read single data byte */
-static unsigned char spi_read(void)
-{
-	unsigned char b = 0;
-
-	/* Set XFER_LENGTH to 1 */
-	REG_CLR(ssp_base + SSP_CTRL0, 0xffff);
-	REG_SET(ssp_base + SSP_CTRL0, 1);
-
-	/* Enable READ mode */
-	REG_SET(ssp_base + SSP_CTRL0, CTRL0_READ);
-
-	/* Set RUN bit */
-	REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN);
-
-
-	/* Set transfer */
-	REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER);
-
-	while (REG_RD(ssp_base + SSP_STATUS) & STATUS_FIFO_EMPTY)
-		;
-
-	/* Read data byte */
-	b = REG_RD(ssp_base + SSP_DATA) & 0xff;
-
-	/* Wait until RUN bit is cleared */
-	while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN)
-			;
-
-	return b;
-}
-
-/* Write single data byte */
-static void spi_write(unsigned char b)
-{
-	/* Set XFER_LENGTH to 1 */
-	REG_CLR(ssp_base + SSP_CTRL0, 0xffff);
-	REG_SET(ssp_base + SSP_CTRL0, 1);
-
-	/* Enable WRITE mode */
-	REG_CLR(ssp_base + SSP_CTRL0, CTRL0_READ);
-
-	/* Set RUN bit */
-	REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN);
-
-	/* Write data byte */
-	REG_WR(ssp_base + SSP_DATA, b);
-
-	/* Set transfer */
-	REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER);
-
-	/* Wait until RUN bit is cleared */
-	while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN)
-		;
-}
-
-static void spi_lock_cs(void)
-{
-	REG_CLR(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC);
-	REG_SET(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS);
-}
-
-static void spi_unlock_cs(void)
-{
-	REG_CLR(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS);
-	REG_SET(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC);
-}
-
-void spi_txrx(const char *dout, unsigned int tx_len, char *din,
-	       unsigned int rx_len, unsigned long flags)
-{
-	int i;
-
-	if (tx_len == 0 && rx_len == 0)
-		return;
-
-	if (flags & SPI_START)
-		spi_lock_cs();
-
-	for (i = 0; i < tx_len; i++) {
-
-		/* Check if it is last data byte to transfer */
-		if (flags & SPI_STOP && rx_len == 0 && i == tx_len - 1)
-			spi_unlock_cs();
-
-		spi_write(dout[i]);
-	}
-
-	for (i = 0; i < rx_len; i++) {
-
-		/* Check if it is last data byte to transfer */
-		if (flags & SPI_STOP && i == rx_len - 1)
-			spi_unlock_cs();
-
-		din[i] = spi_read();
-	}
-}
diff --git a/cpu/arm926ejs/mx28/timer.c b/cpu/arm926ejs/mx28/timer.c
index 873b30c..fef5e7a 100644
--- a/cpu/arm926ejs/mx28/timer.c
+++ b/cpu/arm926ejs/mx28/timer.c
@@ -38,7 +38,6 @@
  */
 
 #include <common.h>
-#include <asm/arch/mx28.h>
 #include <asm/arch/regs-timrot.h>
 
 /*