summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorDavid Brownell <david-b@pacbell.net>2008-01-18 12:55:00 -0800
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-03-30 15:38:05 +0200
commit480ed1dea103a1c8f4591afc77d2de3c7868d983 (patch)
tree3742d043b46f92c9767505d92e6f1ace8bd66954 /cpu
parenta3543d6dc52b0ba9c64016687cf32d600b31a476 (diff)
downloadu-boot-imx-480ed1dea103a1c8f4591afc77d2de3c7868d983.zip
u-boot-imx-480ed1dea103a1c8f4591afc77d2de3c7868d983.tar.gz
u-boot-imx-480ed1dea103a1c8f4591afc77d2de3c7868d983.tar.bz2
use correct at91rm9200 register name
This fixes a naming bug for at91rm9200 lowlevel init code: NOR boot flash is on chipselect 0, not chipselect 2. This makes code use the register name from chip datasheets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/arm920t/at91rm9200/lowlevel_init.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 1902bd0..98363eb 100644
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -46,7 +46,7 @@
#define MC_ASR 0xFFFFFF04
#define MC_AASR 0xFFFFFF08
#define EBI_CFGR 0xFFFFFF64
-#define SMC2_CSR 0xFFFFFF70
+#define SMC_CSR0 0xFFFFFF70
/* clocks */
#define PLLAR 0xFFFFFC28
@@ -146,8 +146,8 @@ SMRDATA:
.word MC_AASR_VAL
.word EBI_CFGR
.word EBI_CFGR_VAL
- .word SMC2_CSR
- .word SMC2_CSR_VAL
+ .word SMC_CSR0
+ .word SMC_CSR0_VAL
.word PLLAR
.word PLLAR_VAL
.word PLLBR