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| author | wdenk <wdenk> | 2005-01-09 18:12:51 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2005-01-09 18:12:51 +0000 |
| commit | 30ce5ab043db0b34838ad2d294561992bdb5236a (patch) | |
| tree | f1897c41bfac1193db786f52eb71854a0c3ef1cc /cpu | |
| parent | 9dd611b8c1db94181918481d5cac1fac241a7954 (diff) | |
| download | u-boot-imx-30ce5ab043db0b34838ad2d294561992bdb5236a.zip u-boot-imx-30ce5ab043db0b34838ad2d294561992bdb5236a.tar.gz u-boot-imx-30ce5ab043db0b34838ad2d294561992bdb5236a.tar.bz2 | |
* Patch by Gleb Natapov, 07 Sep 2004:
mpc824x: set PCI latency timer to a sane value
(is 0 after reset).
* Patch by Kurt Stremerch, 03 Sep 2004:
Add bitstream configuration option for fpga command (Xilinx only).
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc824x/cpu_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c index d0c7a3b..965f4fd 100644 --- a/cpu/mpc824x/cpu_init.c +++ b/cpu/mpc824x/cpu_init.c @@ -90,7 +90,7 @@ cpu_init_f (void) #endif CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ - + CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */ /* * Note that although this bit is cleared after a hard reset, it * must be explicitly set and then cleared by software during |