Patch by Jon Loeliger, 17 June 2004:

Completion of the 8540ADS/8560ADS updates:
Fix some PCI and Rapid I/O memory maps,
Initialize both TSEC 1 and 2,
Initialize SDRAM
Update MAINTAINER for 85xx boards and README.mpc85xxads

3 files changed, 84 insertions, 98 deletions

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 55593d9..8eb9317 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -174,16 +174,6 @@ reset_85xx_watchdog(void)
 #endif	/* CONFIG_WATCHDOG */
 
 #if defined(CONFIG_DDR_ECC)
-__inline__ void dcbz(const void* addr)
-{
-	__asm__ __volatile__ ("dcbz 0,%0" :: "r" (addr));
-}
-
-__inline__ void dcbf(const void* addr)
-{
-	__asm__ __volatile__ ("dcbf 0,%0" :: "r" (addr));
-}
-
 void dma_init(void) {
 	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_dma_t *dma = &immap->im_dma;
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 5732c29..11f0c3e 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2004 Freescale Semiconductor.
  * Copyright (C) 2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
  *
@@ -28,17 +29,23 @@
 #include <asm/cpm_85xx.h>
 #include <pci.h>
 
+
 #if defined(CONFIG_PCI)
+
+
 /*
  * Initialize PCI Devices, report devices found.
  */
+
 #ifndef CONFIG_PCI_PNP
 static struct pci_config_table pci_mpc85xxads_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_IDSEL_NUMBER, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				       PCI_ENET0_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ }
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{}
 };
 #endif
 
@@ -48,60 +55,61 @@ struct pci_controller local_hose = {
 #endif
 };
 
-void pci_init_board(void)
-{
-    struct pci_controller* hose = (struct pci_controller *)&local_hose;
-    volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
-    volatile ccsr_pcix_t *pcix = &immap->im_pcix;
-
-    u16 reg16;
-
-    hose->first_busno = 0;
-    hose->last_busno = 0xff;
-
-    pci_set_region(hose->regions + 0,
-	CFG_PCI_MEM_BASE,
-	CFG_PCI_MEM_PHYS,
-	(CFG_PCI_MEM_SIZE/2),
-	PCI_REGION_MEM);
-
-    pci_set_region(hose->regions + 1,
-	(CFG_PCI_MEM_BASE+0x08000000),
-	(CFG_PCI_MEM_PHYS+0x08000000),
-	0x1000000, /* 16M */
-	PCI_REGION_IO);
-
-    hose->region_count = 2;
-
-    pci_setup_indirect(hose,
-	(CFG_IMMR+0x8000),
-	(CFG_IMMR+0x8004));
-
-    pci_register_hose(hose);
-
-    hose->last_busno = pci_hose_scan(hose);
-
-    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
-    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
-    /* Clear non-reserved bits in status register */
-    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
-    pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-
-    pcix->potar1   = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
-    pcix->potear1  = 0x00000000;
-    pcix->powbar1  = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
-    pcix->powbear1 = 0x00000000;
-    pcix->powar1   = 0x8004401a; /* 128M MEM space */
-    pcix->potar2   = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12)  & 0x000fffff;
-    pcix->potear2  = 0x00000000;
-    pcix->powbar2  = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) && 0x000fffff;
-    pcix->powbear2 = 0x00000000;
-    pcix->powar2   = 0x80088017; /* 16M IO  space */
-    pcix->pitar1 = 0x00000000;
-    pcix->piwbar1 = 0x00000000;
-    pcix->piwar1 = 0xa0F5501f;
 
+void pci_init_board (void)
+{
+	struct pci_controller *hose = (struct pci_controller *) &local_hose;
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_pcix_t *pcix = &immap->im_pcix;
+
+	u16 reg16;
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	pci_set_region (hose->regions + 0,
+			CFG_PCI1_MEM_BASE,
+			CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	pci_set_region (hose->regions + 1,
+			CFG_PCI1_IO_BASE,
+			CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	hose->region_count = 2;
+
+	pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
+
+	pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff);
+	pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80);
+
+	pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+	pcix->potear1 = 0x00000000;
+	pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+	pcix->powbear1 = 0x00000000;
+	pcix->powar1 = 0x8004401c;	/* 512M MEM space */
+
+	pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+	pcix->potear2 = 0x00000000;
+	pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+	pcix->powbear2 = 0x00000000;
+	pcix->powar2 = 0x80088017;	/* 16M IO space */
+
+	pcix->pitar1 = 0x00000000;
+	pcix->piwbar1 = 0x00000000;
+	pcix->piwar1 = 0xa0F5501f;
+
+	/*
+	 * Hose scan.
+	 */
+	pci_register_hose (hose);
+	hose->last_busno = pci_hose_scan (hose);
 }
+
 #endif /* CONFIG_PCI */
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 040b88d..885f1ab 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -130,7 +130,6 @@ _start_e500:
 	/* disable d-cache */
 	li	r0,0x0
 	mtspr	L1CSR0,r0
-	isync
 
 	/* invalidate i-cache */
 	mfspr	r0,L1CSR1
@@ -144,7 +143,6 @@ _start_e500:
 	isync
 
 	/* clear registers */
-	sync
 	li	r0,0
 	mtspr	SRR0,r0
 	mtspr	SRR1,r0
@@ -158,11 +156,8 @@ _start_e500:
 	mtspr	DEAR,r0
 
 	mtspr	DBCR0,r0
-	isync
 	mtspr	DBCR1,r0
-	isync
 	mtspr	DBCR2,r0
-	isync
 	mtspr	IAC1,r0
 	mtspr	IAC2,r0
 	mtspr	DAC1,r0
@@ -171,26 +166,13 @@ _start_e500:
 	mfspr	r1,DBSR
 	mtspr	DBSR,r1		/* Clear all valid bits */
 
-	isync
 	mtspr	PID0,r0
-	isync
 	mtspr	PID1,r0
-	isync
 	mtspr	PID2,r0
-	isync
-
 	mtspr	TCR,r0
 
 	mtspr	BUCSR,r0	/* disable branch prediction */
-	isync
-
-	mtspr	HID0,r0
-	isync
-	mtspr	HID1,r0
-	isync
-
 	mtspr   MAS4,r0
-	isync
 	mtspr   MAS6,r0
 	isync
 
@@ -376,9 +358,9 @@ _start:
 	isync
 
 	/* Enable Time Base and Select Time Base Clock */
-	li	r0,0x4000		/* time base is processor clock */
+	lis	r0,HID0_EMCP@h		/* Enable machine check */
+	ori	r0,r0,0x4000		/* time base is processor clock */
 	mtspr	HID0,r0
-	isync
 
 #if defined(CONFIG_ADDR_STREAMING)
 	li	r0,0x3000
@@ -386,31 +368,26 @@ _start:
 	li	r0,0x1000
 #endif
 	mtspr	HID1,r0
-	isync
 
 	/* Enable Branch Prediction */
 #if defined(CONFIG_BTB)
 	li	r0,0x201		/* BBFI = 1, BPEN = 1 */
 	mtspr	BUCSR,r0
-	isync
 #endif
 
 #if defined(CFG_INIT_DBCR)
 	lis	r1,0xffff
 	ori	r1,r1,0xffff
-	mtspr	dbsr,r1			/* Clear all status bits */
+	mtspr	DBSR,r1			/* Clear all status bits */
 	lis	r0,CFG_INIT_DBCR@h	/* DBCR0[IDM] must be set */
 	ori	r0,r0,CFG_INIT_DBCR@l
-	mtspr	dbcr0,r0
-	isync
+	mtspr	DBCR0,r0
 #endif
 
 /* L1 DCache is used for initial RAM */
 	mfspr	r2, L1CSR0
 	ori    	r2, r2, 0x0003
 	oris   	r2, r2, 0x0001
-	msync
-	isync
 	mtspr  	L1CSR0, r2	/* enable/invalidate L1 Dcache */
 	isync
 
@@ -457,8 +434,7 @@ in_flash:
 	bl	cpu_init_f
 	bl	icache_enable
 	bl	board_init_f
-	sync
-
+	isync
 
 /* --FIXME-- machine check with MCSRRn and rfmci */
 
@@ -922,6 +898,18 @@ ppcDcbi:
 	dcbi	r0,r3
 	blr
 
+/*--------------------------------------------------------------------------
+ * Function:	 ppcDcbz
+ * Description:	 Data Cache block zero.
+ * Input:	 r3 = effective address
+ * Output:	 none.
+ *-------------------------------------------------------------------------- */
+
+	.globl	ppcDcbz
+ppcDcbz:
+	dcbz	r0,r3
+	blr
+
 /*------------------------------------------------------------------------------- */
 /* Function:	 ppcSync */
 /* Description:	 Processor Synchronize */