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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-09-08 08:51:29 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-09-09 16:52:45 -0500 |
| commit | e0ff3d350d6b7960deb5a881dfc5acf3a63ef676 (patch) | |
| tree | bae9341cc649b87241a30b45b5cdb09a67f3627b /cpu | |
| parent | 650a9e7abc44ce1ce73d6668eaf0ba2d6b8025e9 (diff) | |
| download | u-boot-imx-e0ff3d350d6b7960deb5a881dfc5acf3a63ef676.zip u-boot-imx-e0ff3d350d6b7960deb5a881dfc5acf3a63ef676.tar.gz u-boot-imx-e0ff3d350d6b7960deb5a881dfc5acf3a63ef676.tar.bz2 | |
85xx: Ensure timebase is zero on secondary cores
The e500um says the timebase is volatile out of reset. To ensure
TB sync works we need to make sure its zero.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc85xx/release.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 75676b5..ec5e4da 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -37,6 +37,11 @@ __secondary_start_page: li r3,0x201 mtspr SPRN_BUCSR,r3 + /* Ensure TB is 0 */ + li r3,0 + mttbl r3 + mttbu r3 + /* Enable/invalidate the I-Cache */ mfspr r0,SPRN_L1CSR1 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE) |