summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorSergei Poselenov <sposelenov@emcraft.com>2007-07-05 08:17:37 +0200
committerStefan Roese <sr@denx.de>2007-07-05 08:17:37 +0200
commitb44896215a09c60fa40cae906f7ed207bbc2c492 (patch)
treef3c10a507342d083a17dbd7f98e5c662a8f2432e /cpu
parentf780b83316d9af1f61d71cc88b1917b387b9b995 (diff)
downloadu-boot-imx-b44896215a09c60fa40cae906f7ed207bbc2c492.zip
u-boot-imx-b44896215a09c60fa40cae906f7ed207bbc2c492.tar.gz
u-boot-imx-b44896215a09c60fa40cae906f7ed207bbc2c492.tar.bz2
Merged POST framework with the current TOT.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/start.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index dfe813c..6086b6c 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1217,15 +1217,23 @@ mck_return:
* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
* although for some cache-ralated calls stubs have to be provided to satisfy
* symbols resolution.
+ * Icache-related functions are used in POST framework.
*
*/
#ifdef CONFIG_440
.globl dcache_disable
+ .globl icache_disable
+ .globl icache_enable
dcache_disable:
+icache_disable:
+icache_enable:
blr
.globl dcache_status
+ .globl icache_status
dcache_status:
+icache_status:
+ mr r3, 0
blr
#else
flush_dcache: