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| author | Anson Huang <b20788@freescale.com> | 2011-08-22 15:32:10 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2011-08-22 15:33:56 +0800 |
| commit | 4379503e39f059fed62c1f5041e9b99ecb7dd354 (patch) | |
| tree | ff1fd30837c31e03cb1fc6fc292bce2ddef4e45a /cpu | |
| parent | 10ddb7764160b44205152cb52f95986736367f01 (diff) | |
| download | u-boot-imx-4379503e39f059fed62c1f5041e9b99ecb7dd354.zip u-boot-imx-4379503e39f059fed62c1f5041e9b99ecb7dd354.tar.gz u-boot-imx-4379503e39f059fed62c1f5041e9b99ecb7dd354.tar.bz2 | |
ENGR00155156 [MX6]Clean up debug info in uboot
1. ENET don't need to enable ENET pll clock;
2. Enable cpu debug clock in case of using JTAG;
3. Clean up some debug info during bring up.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa8/mx6/generic.c | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c index c2540e1..fb0ef94 100644 --- a/cpu/arm_cortexa8/mx6/generic.c +++ b/cpu/arm_cortexa8/mx6/generic.c @@ -741,31 +741,8 @@ int cpu_eth_init(bd_t *bis) { int rc = -ENODEV; #if defined(CONFIG_MXC_FEC) - printf("cpu_eth_init\n"); rc = mxc_fec_initialize(bis); - /* Set up ENET PLL for 50 MHz */ - - /* Clear power down bit */ - REG_CLR(ANATOP_BASE_ADDR, HW_ANADIG_PLL_ENET, - BM_ANADIG_PLL_ENET_POWERDOWN); - /* Set ENET clock to 50M, Anson need to check */ - REG_SET(ANATOP_BASE_ADDR, HW_ANADIG_PLL_ENET, - BF_ANADIG_PLL_ENET_DIV_SELECT(0x11)); - /* Enable ENET PLL */ - REG_SET(ANATOP_BASE_ADDR, HW_ANADIG_PLL_ENET, - BM_ANADIG_PLL_ENET_ENABLE); - printf("before while\n"); - /* Wait for PLL lock */ - while ((REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_PLL_ENET) & - BM_ANADIG_PLL_ENET_LOCK) == 0) - udelay(100); - /* Clear bypass bit */ - REG_CLR(ANATOP_BASE_ADDR, HW_ANADIG_PLL_ENET, - BM_ANADIG_PLL_ENET_BYPASS); - - printf("before enent_board_init\n"); - /* Board level init */ enet_board_init(); |