ENGR00134068 MX51 BBG:Support CLAA WVGA splashimage

1) IOMUX/backlight support for CLAA WVGA LCD panel.
2) Add video mode for CLAA WVGA LCD panel.
3) Support IPU di1 interface for framebuffer.
4) Enhance IPU driver.
5) Add freescale 600x400 8BPP BMP logo.

Signed-off-by: Terry Lv <R65388@freescale.com>
Signed-off-by: Liu Ying <b17645@freescale.com>

1 files changed, 43 insertions, 0 deletions

diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c
index c26f8ea..cb174ff 100644
--- a/cpu/arm_cortexa8/mx51/generic.c
+++ b/cpu/arm_cortexa8/mx51/generic.c
@@ -1051,3 +1051,46 @@ void enable_usb_phy1_clk(unsigned char enable)
 	writel(reg, MXC_CCM_CCGR2);
 }
 
+void ipu_clk_enable(void)
+{
+	unsigned int reg;
+
+	/* IPU root clock deprived from AXI B */
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
+	reg &= ~0xC0;
+	reg |= 0x40;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CBCMR);
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR5);
+	reg |= (0x3 << 10);
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR5);
+
+	/* Handshake with IPU when certain clock rates are changed. */
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCDR);
+	reg &= ~(0x1 << 17);
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCDR);
+
+	/* Handshake with IPU when LPM is entered as its enabled. */
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CLPCR);
+	reg &= ~(0x1 << 18);
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CLPCR);
+}
+
+void ipu_clk_disable(void)
+{
+	unsigned int reg;
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR5);
+	reg &= (0x3 << 10);
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR5);
+
+	/* Handshake with IPU when certain clock rates are changed. */
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCDR);
+	reg |= (0x1 << 17);
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCDR);
+
+	/* Handshake with IPU when LPM is entered as its enabled. */
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CLPCR);
+	reg |= (0x1 << 18);
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CLPCR);
+}