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authorTerry Lv <r65388@freescale.com>2010-11-17 15:37:49 +0800
committerTerry <r65388@freescale.com>2010-12-14 17:20:40 +0800
commitdca35697e3758ac81894ca305c3f206ff552b697 (patch)
tree02cd77b87c58ea0b0a97d9964a1f869b32e0987f /cpu/sh4/u-boot.lds
parentbb24c00fe03c58f9695b0f68e51f35c6c5982746 (diff)
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ENGR00133727: uart outputs messy code when kernel starts on mx51
uart outputs messy code when kernel starts on mx51. Change uart clock to use pll2 as source clock. Signed-off-by: Terry Lv <r65388@freescale.com>
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