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| author | Andy Fleming <afleming@freescale.com> | 2008-02-27 15:50:50 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-02-27 16:28:57 -0600 |
| commit | 534ea6b6f86f8b75ef2ac061ef110a98f103d7d6 (patch) | |
| tree | 844f1c5f4cdc5a5d2899b14f08741046440887ad /cpu/sh4/cache.c | |
| parent | 21fae8b2b4e4e6e648796e07e20ab13e9cb18923 (diff) | |
| download | u-boot-imx-534ea6b6f86f8b75ef2ac061ef110a98f103d7d6.zip u-boot-imx-534ea6b6f86f8b75ef2ac061ef110a98f103d7d6.tar.gz u-boot-imx-534ea6b6f86f8b75ef2ac061ef110a98f103d7d6.tar.bz2 | |
Fix source for ECM error IVPR
The source vector for the ECM was being set to 2,
but that's what the source vector for DDR was being
set to. Change it to 1.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu/sh4/cache.c')
0 files changed, 0 insertions, 0 deletions