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| author | Stefan Roese <sr@denx.de> | 2009-09-28 17:33:45 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-02 13:53:37 +0200 |
| commit | fb95169e39f2d03270bed552d27bbb02627a443e (patch) | |
| tree | c94e691e322097c7cdc43943cd3bb05b3e7c760e /cpu/s3c44b0/cache.c | |
| parent | d24bd2517a2b847f773453eab0ee5b1c8ebc74ba (diff) | |
| download | u-boot-imx-fb95169e39f2d03270bed552d27bbb02627a443e.zip u-boot-imx-fb95169e39f2d03270bed552d27bbb02627a443e.tar.gz u-boot-imx-fb95169e39f2d03270bed552d27bbb02627a443e.tar.bz2 | |
ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.
Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.
Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
Diffstat (limited to 'cpu/s3c44b0/cache.c')
0 files changed, 0 insertions, 0 deletions