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author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-03-29 23:01:41 +0200 |
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committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-03-29 23:01:41 +0200 |
commit | b2368754a9202225fd072e159fb78da7d2cdb623 (patch) | |
tree | 268ea071f5fb4c508a30712ce890d963c8a27e92 /cpu/s3c44b0/cache.c | |
parent | 40fd626223eae5363719bcb9a6896f08ceeee90a (diff) | |
download | u-boot-imx-b2368754a9202225fd072e159fb78da7d2cdb623.zip u-boot-imx-b2368754a9202225fd072e159fb78da7d2cdb623.tar.gz u-boot-imx-b2368754a9202225fd072e159fb78da7d2cdb623.tar.bz2 |
s3c44b0: extract cache from cpu.c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/s3c44b0/cache.c')
-rw-r--r-- | cpu/s3c44b0/cache.c | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/cpu/s3c44b0/cache.c b/cpu/s3c44b0/cache.c new file mode 100644 index 0000000..bc10171 --- /dev/null +++ b/cpu/s3c44b0/cache.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/hardware.h> + +static void s3c44b0_flush_cache(void) +{ + volatile int i; + /* flush cycle */ + for(i=0x10002000;i<0x10004800;i+=16) + { + *((int *)i)=0x0; + } +} + +void icache_enable (void) +{ + ulong reg; + + s3c44b0_flush_cache(); + + /* + Init cache + Non-cacheable area (everything outside RAM) + 0x0000:0000 - 0x0C00:0000 + */ + NCACHBE0 = 0xC0000000; + NCACHBE1 = 0x00000000; + + /* + Enable chache + */ + reg = SYSCFG; + reg |= 0x00000006; /* 8kB */ + SYSCFG = reg; +} + +void icache_disable (void) +{ + ulong reg; + + reg = SYSCFG; + reg &= ~0x00000006; /* 8kB */ + SYSCFG = reg; +} + +int icache_status (void) +{ + return 0; +} + +void dcache_enable (void) +{ + icache_enable(); +} + +void dcache_disable (void) +{ + icache_disable(); +} + +int dcache_status (void) +{ + return dcache_status(); +} + |