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authorWolfgang Denk <wd@denx.de>2009-04-05 23:04:30 +0200
committerWolfgang Denk <wd@denx.de>2009-04-05 23:04:30 +0200
commit712ac6a1a6909a58d6549fb220cc921a7e9f9979 (patch)
tree7391a68d2b81d9a9096e170b97bbfe0ed81c2c7f /cpu/pxa
parent23e4af49e066a53cd3e3659b68ef90572d88de84 (diff)
parentc6fadb9c73a6a3e0c7f20696e978304a593a8d2d (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'cpu/pxa')
-rw-r--r--cpu/pxa/cpu.c81
1 files changed, 9 insertions, 72 deletions
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index e84cb5b..3a1be57 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -33,11 +33,14 @@
#include <common.h>
#include <command.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/system.h>
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif
+static void cache_flush(void);
+
int cpu_init (void)
{
/*
@@ -59,92 +62,26 @@ int cleanup_before_linux (void)
* just disable everything that can disturb booting linux
*/
- unsigned long i;
-
disable_interrupts ();
/* turn off I-cache */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~0x1000;
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ icache_disable();
+ dcache_disable();
/* flush I-cache */
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+ cache_flush();
return (0);
}
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/* flush I/D-cache */
+static void cache_flush (void)
{
- printf ("resetting ...\n");
-
- udelay (50000); /* wait 50 ms */
- disable_interrupts ();
- reset_cpu (0);
-
- /*NOTREACHED*/
- return (0);
-}
-
-/* taken from blob */
-void icache_enable (void)
-{
- register u32 i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- /* set i-cache */
- i |= 0x1000;
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void icache_disable (void)
-{
- register u32 i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ unsigned long i = 0;
- /* clear i-cache */
- i &= ~0x1000;
-
- /* write back to control register */
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
- /* flush i-cache */
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}
-int icache_status (void)
-{
- register u32 i;
-
- /* read control register */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
- /* return bit */
- return (i & 0x1000);
-}
-
-/* we will never enable dcache, because we have to setup MMU first */
-void dcache_enable (void)
-{
- return;
-}
-
-void dcache_disable (void)
-{
- return;
-}
-
-int dcache_status (void)
-{
- return 0; /* always off */
-}
-
#ifndef CONFIG_CPU_MONAHANS
void set_GPIO_mode(int gpio_mode)
{