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| author | stroese <stroese> | 2003-03-20 15:21:50 +0000 |
|---|---|---|
| committer | stroese <stroese> | 2003-03-20 15:21:50 +0000 |
| commit | 38daa27d21c975c3285933e86c556d1dc69642f9 (patch) | |
| tree | 61f5e150110be10fd912b7271fe5cad94bcc5cdc /cpu/ppc4xx | |
| parent | 1957dd29d980ecb197c3a6dbe4f6609dae135a1d (diff) | |
| download | u-boot-imx-38daa27d21c975c3285933e86c556d1dc69642f9.zip u-boot-imx-38daa27d21c975c3285933e86c556d1dc69642f9.tar.gz u-boot-imx-38daa27d21c975c3285933e86c556d1dc69642f9.tar.bz2 | |
Set edge conditioning circuitry on PPC405GPr for compatibility to existing PPC405GP designs.
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/cpu_init.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 52d4650..9bf180f 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -124,6 +124,7 @@ int cpu_init_r (void) bd_t *bd = gd->bd; unsigned long reg; + uint pvr = get_pvr(); /* * Write Ethernetaddress into on-chip register @@ -143,6 +144,15 @@ int cpu_init_r (void) reg = reg << 8; reg |= bd->bi_enetaddr[5]; out32 (EMAC_IAL, reg); + + /* + * Set edge conditioning circuitry on PPC405GPr + * for compatibility to existing PPC405GP designs. + */ + if ((pvr & 0xfffffff0) == (PVR_405GPR_RA & 0xfffffff0)) { + mtdcr(ecr, 0x60606000); + } + #endif /* CONFIG_405GP */ return (0); } |