Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

29 files changed, 2050 insertions, 2652 deletions

diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index b21b13e..57861b3 100644
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -52,12 +52,12 @@
 /*
  * Set default values
  */
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED	50000
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED	50000
 #endif
 
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE	0xFE
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE	0xFE
 #endif
 
 #define ONE_BILLION	1000000000
@@ -163,7 +163,7 @@ long int spd_sdram(int(read_spd)(uint addr))
 		 * Make sure I2C controller is initialized
 		 * before continuing.
 		 */
-		i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	}
 
 	/* Make shure we are using SDRAM */
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index 9efcede..153391e 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -62,12 +62,12 @@
 /*
  * Set default values
  */
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED	50000
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED	50000
 #endif
 
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE	0xFE
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE	0xFE
 #endif
 
 #define ONE_BILLION	1000000000
@@ -119,7 +119,7 @@ struct bank_param {
 
 typedef struct bank_param BANKPARMS;
 
-#ifdef CFG_SIMULATE_SPD_EEPROM
+#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
 extern const unsigned char cfg_simulate_spd_eeprom[128];
 #endif
 
@@ -174,7 +174,7 @@ long int spd_sdram(void) {
 	 * Make sure I2C controller is initialized
 	 * before continuing.
 	 */
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/*
 	 * Read the SPD information using I2C interface. Check to see if the
@@ -265,7 +265,7 @@ long int spd_sdram(void) {
 	/*
 	 * If ecc is enabled, initialize the parity bits.
 	 */
-	ecc_init(CFG_SDRAM_BASE, total_size);
+	ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
 #endif
 
 	return total_size;
@@ -275,14 +275,14 @@ static unsigned char spd_read(uchar chip, uint addr)
 {
 	unsigned char data[2];
 
-#ifdef CFG_SIMULATE_SPD_EEPROM
-	if (chip == CFG_SIMULATE_SPD_EEPROM) {
+#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
+	if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
 		/*
 		 * Onboard spd eeprom requested -> simulate values
 		 */
 		return cfg_simulate_spd_eeprom[addr];
 	}
-#endif /* CFG_SIMULATE_SPD_EEPROM */
+#endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
 
 	if (i2c_probe(chip) == 0) {
 		if (i2c_read(chip, addr, 1, data, 1) == 0) {
@@ -1120,7 +1120,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
 	/*
 	 * reset the bank_base address
 	 */
-	bank_base_addr = CFG_SDRAM_BASE;
+	bank_base_addr = CONFIG_SYS_SDRAM_BASE;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		if (dimm_populated[dimm_num] == TRUE) {
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 15250d4..b40e4b1 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -60,7 +60,25 @@
 		       "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);	\
 	} while (0)
 
-static inline void ppc4xx_ibm_ddr2_register_dump(void);
+#if defined(CONFIG_440)
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
+ * memory region. Right now the cache should still be disabled in U-Boot
+ * because of the EMAC driver, that need its buffer descriptor to be located
+ * in non cached memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CONFIG_4xx_DCACHE
+/* enable caching on SDRAM */
+#define MY_TLB_WORD2_I_ENABLE		0
+#else
+/* disable caching on SDRAM */
+#define MY_TLB_WORD2_I_ENABLE		TLB_WORD2_I_ENABLE
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_440 */
 
 #if defined(CONFIG_SPD_EEPROM)
 
@@ -133,22 +151,6 @@ static inline void ppc4xx_ibm_ddr2_register_dump(void);
 #define NUMLOOPS	64		/* memory test loops */
 
 /*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
-#endif
-
-/*
  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
  * To support such configurations, we "only" map the first 2GB via the TLB's. We
  * need some free virtual address space for the remaining peripherals like, SoC
@@ -260,62 +262,19 @@ static void program_ecc_addr(unsigned long start_address,
 			     unsigned long num_bytes,
 			     unsigned long tlb_word2_i_value);
 #endif
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 static void program_DQS_calibration(unsigned long *dimm_populated,
-				    unsigned char *iic0_dimm_addr,
-				    unsigned long num_dimm_banks);
+				unsigned char *iic0_dimm_addr,
+				unsigned long num_dimm_banks);
 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 static void	test(void);
 #else
 static void	DQS_calibration_process(void);
 #endif
+#endif
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 void dcbz_area(u32 start_address, u32 num_bytes);
 
-static u32 mfdcr_any(u32 dcr)
-{
-	u32 val;
-
-	switch (dcr) {
-	case SDRAM_R0BAS + 0:
-		val = mfdcr(SDRAM_R0BAS + 0);
-		break;
-	case SDRAM_R0BAS + 1:
-		val = mfdcr(SDRAM_R0BAS + 1);
-		break;
-	case SDRAM_R0BAS + 2:
-		val = mfdcr(SDRAM_R0BAS + 2);
-		break;
-	case SDRAM_R0BAS + 3:
-		val = mfdcr(SDRAM_R0BAS + 3);
-		break;
-	default:
-		printf("DCR %d not defined in case statement!!!\n", dcr);
-		val = 0; /* just to satisfy the compiler */
-	}
-
-	return val;
-}
-
-static void mtdcr_any(u32 dcr, u32 val)
-{
-	switch (dcr) {
-	case SDRAM_R0BAS + 0:
-		mtdcr(SDRAM_R0BAS + 0, val);
-		break;
-	case SDRAM_R0BAS + 1:
-		mtdcr(SDRAM_R0BAS + 1, val);
-		break;
-	case SDRAM_R0BAS + 2:
-		mtdcr(SDRAM_R0BAS + 2, val);
-		break;
-	case SDRAM_R0BAS + 3:
-		mtdcr(SDRAM_R0BAS + 3, val);
-		break;
-	default:
-		printf("DCR %d not defined in case statement!!!\n", dcr);
-	}
-}
-
 static unsigned char spd_read(uchar chip, uint addr)
 {
 	unsigned char data[2];
@@ -447,8 +406,8 @@ phys_size_t initdram(int board_type)
 	 */
 
 	/* switch to correct I2C bus */
-	I2C_SET_BUS(CFG_SPD_BUS_NUM);
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/*------------------------------------------------------------------
 	 * Clear out the serial presence detect buffers.
@@ -609,7 +568,11 @@ phys_size_t initdram(int board_type)
 	/*------------------------------------------------------------------
 	 * DQS calibration.
 	 *-----------------------------------------------------------------*/
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+	DQS_autocalibration();
+#else
 	program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+#endif
 
 #ifdef CONFIG_DDR_ECC
 	/*------------------------------------------------------------------
@@ -2302,10 +2265,12 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	/*
 	 * Set optimal value for Memory Queue HB/LL Configuration registers
 	 */
-	mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
-	      SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
-	mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
-	      SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+	mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
+	      SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
+	      SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
+	mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
+	      SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
+	      SDRAM_CONF1LL_RPLM);
 	mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
 #endif
 }
@@ -2329,18 +2294,6 @@ static unsigned long is_ecc_enabled(void)
 	return ecc;
 }
 
-static void blank_string(int size)
-{
-	int i;
-
-	for (i=0; i<size; i++)
-		putc('\b');
-	for (i=0; i<size; i++)
-		putc(' ');
-	for (i=0; i<size; i++)
-		putc('\b');
-}
-
 #ifdef CONFIG_DDR_ECC
 /*-----------------------------------------------------------------------------+
  * program_ecc.
@@ -2468,6 +2421,7 @@ static void program_ecc_addr(unsigned long start_address,
 }
 #endif
 
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 /*-----------------------------------------------------------------------------+
  * program_DQS_calibration.
  *-----------------------------------------------------------------------------*/
@@ -3001,15 +2955,17 @@ static void test(void)
 		(ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
 		| ecc_temp);
 }
-#endif
+#endif /* !HARD_CODED_DQS */
+#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
 
 #else /* CONFIG_SPD_EEPROM */
 
 /*-----------------------------------------------------------------------------
  * Function:	initdram
- * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
- * 		banks. The configuration is performed using static, compile-
+ * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
+ * 		The configuration is performed using static, compile-
  *		time parameters.
+ * 		Configures the PPC405EX(r) and PPC460EX/GT
  *---------------------------------------------------------------------------*/
 phys_size_t initdram(int board_type)
 {
@@ -3025,64 +2981,76 @@ phys_size_t initdram(int board_type)
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 	unsigned long val;
 
+#if defined(CONFIG_440)
+	mtdcr(SDRAM_R0BAS,	CONFIG_SYS_SDRAM_R0BAS);
+	mtdcr(SDRAM_R1BAS,	CONFIG_SYS_SDRAM_R1BAS);
+	mtdcr(SDRAM_R2BAS,	CONFIG_SYS_SDRAM_R2BAS);
+	mtdcr(SDRAM_R3BAS,	CONFIG_SYS_SDRAM_R3BAS);
+	mtdcr(SDRAM_PLBADDULL,	CONFIG_SYS_SDRAM_PLBADDULL);	/* MQ0_BAUL */
+	mtdcr(SDRAM_PLBADDUHB,	CONFIG_SYS_SDRAM_PLBADDUHB);	/* MQ0_BAUH */
+	mtdcr(SDRAM_CONF1LL,	CONFIG_SYS_SDRAM_CONF1LL);
+	mtdcr(SDRAM_CONF1HB,	CONFIG_SYS_SDRAM_CONF1HB);
+	mtdcr(SDRAM_CONFPATHB,	CONFIG_SYS_SDRAM_CONFPATHB);
+#endif
+
 	/* Set Memory Bank Configuration Registers */
 
-	mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
-	mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
-	mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
-	mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+	mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
+	mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
+	mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
+	mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
 
 	/* Set Memory Clock Timing Register */
 
-	mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+	mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
 
 	/* Set Refresh Time Register */
 
-	mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
+	mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
 
 	/* Set SDRAM Timing Registers */
 
-	mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
-	mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
-	mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+	mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
+	mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
+	mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
 
 	/* Set Mode and Extended Mode Registers */
 
-	mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
-	mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+	mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
+	mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
 
 	/* Set Memory Controller Options 1 Register */
 
-	mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+	mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
 
 	/* Set Manual Initialization Control Registers */
 
-	mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
-	mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
-	mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
-	mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
-	mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
-	mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
-	mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
-	mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
-	mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
-	mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
-	mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
-	mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
-	mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
-	mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
-	mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
-	mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+	mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
+	mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
+	mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
+	mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
+	mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
+	mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
+	mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
+	mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
+	mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
+	mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
+	mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
+	mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
+	mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
+	mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
+	mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
+	mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
 
 	/* Set On-Die Termination Registers */
 
-	mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
-	mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
-	mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+	mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
+	mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
+	mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
 
 	/* Set Write Timing Register */
 
-	mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
+	mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
 
 	/*
 	 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
@@ -3103,10 +3071,13 @@ phys_size_t initdram(int board_type)
 
 	/* Set Delay Control Registers */
 
-	mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
-	mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
-	mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
-	mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
+	mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
+
+#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+	mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
+	mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
+	mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
+#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
 	/*
 	 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
@@ -3115,18 +3086,116 @@ phys_size_t initdram(int board_type)
 	mfsdram(SDRAM_MCOPT2, val);
 	mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
 
+#if defined(CONFIG_440)
+	/*
+	 * Program TLB entries with caches enabled, for best performace
+	 * while auto-calibrating and ECC generation
+	 */
+	program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
+#endif
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*------------------------------------------------------------------
+	 | DQS calibration.
+	 +-----------------------------------------------------------------*/
+	DQS_autocalibration();
+#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
+#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
+
 #if defined(CONFIG_DDR_ECC)
-	ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+	ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
 #endif /* defined(CONFIG_DDR_ECC) */
 
+#if defined(CONFIG_440)
+	/*
+	 * Now after initialization (auto-calibration and ECC generation)
+	 * remove the TLB entries with caches enabled and program again with
+	 * desired cache functionality
+	 */
+	remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
+	program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
+#endif
+
 	ppc4xx_ibm_ddr2_register_dump();
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
+
 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 
-	return (CFG_MBYTES_SDRAM << 20);
+	return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }
 #endif /* CONFIG_SPD_EEPROM */
 
-static inline void ppc4xx_ibm_ddr2_register_dump(void)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_440)
+u32 mfdcr_any(u32 dcr)
+{
+	u32 val;
+
+	switch (dcr) {
+	case SDRAM_R0BAS + 0:
+		val = mfdcr(SDRAM_R0BAS + 0);
+		break;
+	case SDRAM_R0BAS + 1:
+		val = mfdcr(SDRAM_R0BAS + 1);
+		break;
+	case SDRAM_R0BAS + 2:
+		val = mfdcr(SDRAM_R0BAS + 2);
+		break;
+	case SDRAM_R0BAS + 3:
+		val = mfdcr(SDRAM_R0BAS + 3);
+		break;
+	default:
+		printf("DCR %d not defined in case statement!!!\n", dcr);
+		val = 0; /* just to satisfy the compiler */
+	}
+
+	return val;
+}
+
+void mtdcr_any(u32 dcr, u32 val)
+{
+	switch (dcr) {
+	case SDRAM_R0BAS + 0:
+		mtdcr(SDRAM_R0BAS + 0, val);
+		break;
+	case SDRAM_R0BAS + 1:
+		mtdcr(SDRAM_R0BAS + 1, val);
+		break;
+	case SDRAM_R0BAS + 2:
+		mtdcr(SDRAM_R0BAS + 2, val);
+		break;
+	case SDRAM_R0BAS + 3:
+		mtdcr(SDRAM_R0BAS + 3, val);
+		break;
+	default:
+		printf("DCR %d not defined in case statement!!!\n", dcr);
+	}
+}
+#endif /* defined(CONFIG_440) */
+
+void blank_string(int size)
+{
+	int i;
+
+	for (i = 0; i < size; i++)
+		putc('\b');
+	for (i = 0; i < size; i++)
+		putc(' ');
+	for (i = 0; i < size; i++)
+		putc('\b');
+}
+#endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
+
+inline void ppc4xx_ibm_ddr2_register_dump(void)
 {
 #if defined(DEBUG)
 	printf("\nPPC4xx IBM DDR2 Register Dump:\n");
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
deleted file mode 100644
index 8a38335..0000000
--- a/cpu/ppc4xx/4xx_enet.c
+++ /dev/null
@@ -1,1983 +0,0 @@
-/*-----------------------------------------------------------------------------+
- *
- *	 This source code has been made available to you by IBM on an AS-IS
- *	 basis.	 Anyone receiving this source is licensed under IBM
- *	 copyrights to use it in any way he or she deems fit, including
- *	 copying it, modifying it, compiling it, and redistributing it either
- *	 with or without modifications.	 No license under IBM patents or
- *	 patent applications is to be implied by the copyright license.
- *
- *	 Any user of this software should understand that IBM cannot provide
- *	 technical support for this software and will not be responsible for
- *	 any consequences resulting from the use of this software.
- *
- *	 Any person who transfers this source code or any derivative work
- *	 must include the IBM copyright notice, this paragraph, and the
- *	 preceding two paragraphs in the transferred software.
- *
- *	 COPYRIGHT   I B M   CORPORATION 1995
- *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
- *-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
- *
- *  File Name:	enetemac.c
- *
- *  Function:	Device driver for the ethernet EMAC3 macro on the 405GP.
- *
- *  Author:	Mark Wisner
- *
- *  Change Activity-
- *
- *  Date	Description of Change					    BY
- *  ---------	---------------------					    ---
- *  05-May-99	Created							    MKW
- *  27-Jun-99	Clean up						    JWB
- *  16-Jul-99	Added MAL error recovery and better IP packet handling	    MKW
- *  29-Jul-99	Added Full duplex support				    MKW
- *  06-Aug-99	Changed names for Mal CR reg				    MKW
- *  23-Aug-99	Turned off SYE when running at 10Mbs			    MKW
- *  24-Aug-99	Marked descriptor empty after call_xlc			    MKW
- *  07-Sep-99	Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16	    MCG
- *		to avoid chaining maximum sized packets. Push starting
- *		RX descriptor address up to the next cache line boundary.
- *  16-Jan-00	Added support for booting with IP of 0x0		    MKW
- *  15-Mar-00	Updated enetInit() to enable broadcast addresses in the
- *		EMAC_RXM register.					    JWB
- *  12-Mar-01	anne-sophie.harnois@nextream.fr
- *		 - Variables are compatible with those already defined in
- *		  include/net.h
- *		- Receive buffer descriptor ring is used to send buffers
- *		  to the user
- *		- Info print about send/received/handled packet number if
- *		  INFO_405_ENET is set
- *  17-Apr-01	stefan.roese@esd-electronics.com
- *		- MAL reset in "eth_halt" included
- *		- Enet speed and duplex output now in one line
- *  08-May-01	stefan.roese@esd-electronics.com
- *		- MAL error handling added (eth_init called again)
- *  13-Nov-01	stefan.roese@esd-electronics.com
- *		- Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
- *  04-Jan-02	stefan.roese@esd-electronics.com
- *		- Wait for PHY auto negotiation to complete added
- *  06-Feb-02	stefan.roese@esd-electronics.com
- *		- Bug fixed in waiting for auto negotiation to complete
- *  26-Feb-02	stefan.roese@esd-electronics.com
- *		- rx and tx buffer descriptors now allocated (no fixed address
- *		  used anymore)
- *  17-Jun-02	stefan.roese@esd-electronics.com
- *		- MAL error debug printf 'M' removed (rx de interrupt may
- *		  occur upon many incoming packets with only 4 rx buffers).
- *-----------------------------------------------------------------------------*
- *  17-Nov-03	travis.sawyer@sandburst.com
- *		- ported from 405gp_enet.c to utilized upto 4 EMAC ports
- *		  in the 440GX.	 This port should work with the 440GP
- *		  (2 EMACs) also
- *  15-Aug-05	sr@denx.de
- *		- merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
-		  now handling all 4xx cpu's.
- *-----------------------------------------------------------------------------*/
-
-#include <config.h>
-#include <common.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <commproc.h>
-#include <ppc4xx.h>
-#include <ppc4xx_enet.h>
-#include <405_mal.h>
-#include <miiphy.h>
-#include <malloc.h>
-
-/*
- * Only compile for platform with AMCC EMAC ethernet controller and
- * network support enabled.
- * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
- */
-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
-
-#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
-#error "CONFIG_MII has to be defined!"
-#endif
-
-#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
-#error "CONFIG_NET_MULTI has to be defined for NetConsole"
-#endif
-
-#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 5000	/* 5000 ms autonegotiate timeout */
-
-/* Ethernet Transmit and Receive Buffers */
-/* AS.HARNOIS
- * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
- * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
- */
-#define ENET_MAX_MTU	       PKTSIZE
-#define ENET_MAX_MTU_ALIGNED   PKTSIZE_ALIGN
-
-/*-----------------------------------------------------------------------------+
- * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
- * Interrupt Controller).
- *-----------------------------------------------------------------------------*/
-#define ETH_IRQ_NUM(dev)	(VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
-
-#if defined(CONFIG_HAS_ETH3)
-#if !defined(CONFIG_440GX)
-#define UIC_ETHx	(UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
-			 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
-#else
-/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
-#define UIC_ETHx	(UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
-#define UIC_ETHxB	(UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
-#endif /* !defined(CONFIG_440GX) */
-#elif defined(CONFIG_HAS_ETH2)
-#define UIC_ETHx	(UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
-			 UIC_MASK(ETH_IRQ_NUM(2)))
-#elif defined(CONFIG_HAS_ETH1)
-#define UIC_ETHx	(UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
-#else
-#define UIC_ETHx	UIC_MASK(ETH_IRQ_NUM(0))
-#endif
-
-/*
- * Define a default version for UIC_ETHxB for non 440GX so that we can
- * use common code for all 4xx variants
- */
-#if !defined(UIC_ETHxB)
-#define UIC_ETHxB	0
-#endif
-
-#define UIC_MAL_SERR	UIC_MASK(VECNUM_MAL_SERR)
-#define UIC_MAL_TXDE	UIC_MASK(VECNUM_MAL_TXDE)
-#define UIC_MAL_RXDE	UIC_MASK(VECNUM_MAL_RXDE)
-#define UIC_MAL_TXEOB	UIC_MASK(VECNUM_MAL_TXEOB)
-#define UIC_MAL_RXEOB	UIC_MASK(VECNUM_MAL_RXEOB)
-
-#define MAL_UIC_ERR	(UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
-#define MAL_UIC_DEF	(UIC_MAL_RXEOB | MAL_UIC_ERR)
-
-/*
- * We have 3 different interrupt types:
- * - MAL interrupts indicating successful transfer
- * - MAL error interrupts indicating MAL related errors
- * - EMAC interrupts indicating EMAC related errors
- *
- * All those interrupts can be on different UIC's, but since
- * now at least all interrupts from one type are on the same
- * UIC. Only exception is 440GX where the EMAC interrupts are
- * spread over two UIC's!
- */
-#if defined(CONFIG_440GX)
-#define UIC_BASE_MAL	UIC1_DCR_BASE
-#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
-#define UIC_BASE_EMAC	UIC2_DCR_BASE
-#define UIC_BASE_EMAC_B	UIC3_DCR_BASE
-#else
-#define UIC_BASE_MAL	(UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
-#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
-#define UIC_BASE_EMAC	(UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
-#define UIC_BASE_EMAC_B	(UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
-#endif
-
-#undef INFO_4XX_ENET
-
-#define BI_PHYMODE_NONE	 0
-#define BI_PHYMODE_ZMII	 1
-#define BI_PHYMODE_RGMII 2
-#define BI_PHYMODE_GMII  3
-#define BI_PHYMODE_RTBI  4
-#define BI_PHYMODE_TBI   5
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-#define BI_PHYMODE_SMII  6
-#define BI_PHYMODE_MII   7
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define BI_PHYMODE_RMII  8
-#endif
-#endif
-
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-#define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define SDR0_ETH_CFG_CLK_SEL_V(n)	(0x01 << (8 + n))
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define MAL_RX_CHAN_MUL	8	/* 460EX/GT uses MAL channel 8 for EMAC1 */
-#else
-#define MAL_RX_CHAN_MUL	1
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Global variables. TX and RX descriptors and buffers.
- *-----------------------------------------------------------------------------*/
-#if !defined(CONFIG_NET_MULTI)
-struct eth_device *emac0_dev = NULL;
-#endif
-
-/*
- * Get count of EMAC devices (doesn't have to be the max. possible number
- * supported by the cpu)
- *
- * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
- * EMAC count is possible. As it is needed for the Kilauea/Haleakala
- * 405EX/405EXr eval board, using the same binary.
- */
-#if defined(CONFIG_BOARD_EMAC_COUNT)
-#define LAST_EMAC_NUM	board_emac_count()
-#else /* CONFIG_BOARD_EMAC_COUNT */
-#if defined(CONFIG_HAS_ETH3)
-#define LAST_EMAC_NUM	4
-#elif defined(CONFIG_HAS_ETH2)
-#define LAST_EMAC_NUM	3
-#elif defined(CONFIG_HAS_ETH1)
-#define LAST_EMAC_NUM	2
-#else
-#define LAST_EMAC_NUM	1
-#endif
-#endif /* CONFIG_BOARD_EMAC_COUNT */
-
-/* normal boards start with EMAC0 */
-#if !defined(CONFIG_EMAC_NR_START)
-#define CONFIG_EMAC_NR_START	0
-#endif
-
-#define MAL_RX_DESC_SIZE	2048
-#define MAL_TX_DESC_SIZE	2048
-#define MAL_ALLOC_SIZE		(MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
-
-/*-----------------------------------------------------------------------------+
- * Prototypes and externals.
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr);
-
-int enetInt (struct eth_device *dev);
-static void mal_err (struct eth_device *dev, unsigned long isr,
-		     unsigned long uic, unsigned long maldef,
-		     unsigned long mal_errr);
-static void emac_err (struct eth_device *dev, unsigned long isr);
-
-extern int phy_setup_aneg (char *devname, unsigned char addr);
-extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short *value);
-extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value);
-
-int board_emac_count(void);
-
-static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
-{
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_405EX)
-	u32 val;
-
-	mfsdr(sdr_mfr, val);
-	val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
-	mtsdr(sdr_mfr, val);
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	u32 val;
-
-	mfsdr(SDR0_ETH_CFG, val);
-	val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
-	mtsdr(SDR0_ETH_CFG, val);
-#endif
-}
-
-static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
-{
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_405EX)
-	u32 val;
-
-	mfsdr(sdr_mfr, val);
-	val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
-	mtsdr(sdr_mfr, val);
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	u32 val;
-
-	mfsdr(SDR0_ETH_CFG, val);
-	val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
-	mtsdr(SDR0_ETH_CFG, val);
-#endif
-}
-
-/*-----------------------------------------------------------------------------+
-| ppc_4xx_eth_halt
-| Disable MAL channel, and EMACn
-+-----------------------------------------------------------------------------*/
-static void ppc_4xx_eth_halt (struct eth_device *dev)
-{
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-	u32 val = 10000;
-
-	out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000);	/* disable emac interrupts */
-
-	/* 1st reset MAL channel */
-	/* Note: writing a 0 to a channel has no effect */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
-#else
-	mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
-#endif
-	mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
-
-	/* wait for reset */
-	while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
-		udelay (1000);	/* Delay 1 MS so as not to hammer the register */
-		val--;
-		if (val == 0)
-			break;
-	}
-
-	/* provide clocks for EMAC internal loopback  */
-	emac_loopback_enable(hw_p);
-
-	/* EMAC RESET */
-	out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-
-	/* remove clocks for EMAC internal loopback  */
-	emac_loopback_disable(hw_p);
-
-#ifndef CONFIG_NETCONSOLE
-	hw_p->print_speed = 1;	/* print speed message again next time */
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	/* don't bypass the TAHOE0/TAHOE1 cores for Linux */
-	mfsdr(SDR0_ETH_CFG, val);
-	val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
-	mtsdr(SDR0_ETH_CFG, val);
-#endif
-
-	return;
-}
-
-#if defined (CONFIG_440GX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
-	unsigned long pfc1;
-	unsigned long zmiifer;
-	unsigned long rmiifer;
-
-	mfsdr(sdr_pfc1, pfc1);
-	pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
-
-	zmiifer = 0;
-	rmiifer = 0;
-
-	switch (pfc1) {
-	case 1:
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
-		break;
-	case 2:
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
-		break;
-	case 3:
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		break;
-	case 4:
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
-		break;
-	case 5:
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
-		break;
-	case 6:
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
-		break;
-	case 0:
-	default:
-		zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
-		rmiifer = 0x0;
-		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
-		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
-		break;
-	}
-
-	/* Ensure we setup mdio for this devnum and ONLY this devnum */
-	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
-
-	out_be32((void *)ZMII_FER, zmiifer);
-	out_be32((void *)RGMII_FER, rmiifer);
-
-	return ((int)pfc1);
-}
-#endif	/* CONFIG_440_GX */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
-	unsigned long zmiifer=0x0;
-	unsigned long pfc1;
-
-	mfsdr(sdr_pfc1, pfc1);
-	pfc1 &= SDR0_PFC1_SELECT_MASK;
-
-	switch (pfc1) {
-	case SDR0_PFC1_SELECT_CONFIG_2:
-		/* 1 x GMII port */
-		out_be32((void *)ZMII_FER, 0x00);
-		out_be32((void *)RGMII_FER, 0x00000037);
-		bis->bi_phymode[0] = BI_PHYMODE_GMII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		break;
-	case SDR0_PFC1_SELECT_CONFIG_4:
-		/* 2 x RGMII ports */
-		out_be32((void *)ZMII_FER, 0x00);
-		out_be32((void *)RGMII_FER, 0x00000055);
-		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
-		break;
-	case SDR0_PFC1_SELECT_CONFIG_6:
-		/* 2 x SMII ports */
-		out_be32((void *)ZMII_FER,
-			 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
-			 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
-		out_be32((void *)RGMII_FER, 0x00000000);
-		bis->bi_phymode[0] = BI_PHYMODE_SMII;
-		bis->bi_phymode[1] = BI_PHYMODE_SMII;
-		break;
-	case SDR0_PFC1_SELECT_CONFIG_1_2:
-		/* only 1 x MII supported */
-		out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
-		out_be32((void *)RGMII_FER, 0x00000000);
-		bis->bi_phymode[0] = BI_PHYMODE_MII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		break;
-	default:
-		break;
-	}
-
-	/* Ensure we setup mdio for this devnum and ONLY this devnum */
-	zmiifer = in_be32((void *)ZMII_FER);
-	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
-	out_be32((void *)ZMII_FER, zmiifer);
-
-	return ((int)0x0);
-}
-#endif	/* CONFIG_440EPX */
-
-#if defined(CONFIG_405EX)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
-	u32 rgmiifer = 0;
-
-	/*
-	 * The 405EX(r)'s RGMII bridge can operate in one of several
-	 * modes, only one of which (2 x RGMII) allows the
-	 * simultaneous use of both EMACs on the 405EX.
-	 */
-
-	switch (CONFIG_EMAC_PHY_MODE) {
-
-	case EMAC_PHY_MODE_NONE:
-		/* No ports */
-		rgmiifer |= RGMII_FER_DIS	<< 0;
-		rgmiifer |= RGMII_FER_DIS	<< 4;
-		out_be32((void *)RGMII_FER, rgmiifer);
-		bis->bi_phymode[0] = BI_PHYMODE_NONE;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		break;
-	case EMAC_PHY_MODE_NONE_RGMII:
-		/* 1 x RGMII port on channel 0 */
-		rgmiifer |= RGMII_FER_RGMII	<< 0;
-		rgmiifer |= RGMII_FER_DIS	<< 4;
-		out_be32((void *)RGMII_FER, rgmiifer);
-		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		break;
-	case EMAC_PHY_MODE_RGMII_NONE:
-		/* 1 x RGMII port on channel 1 */
-		rgmiifer |= RGMII_FER_DIS	<< 0;
-		rgmiifer |= RGMII_FER_RGMII	<< 4;
-		out_be32((void *)RGMII_FER, rgmiifer);
-		bis->bi_phymode[0] = BI_PHYMODE_NONE;
-		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
-		break;
-	case EMAC_PHY_MODE_RGMII_RGMII:
-		/* 2 x RGMII ports */
-		rgmiifer |= RGMII_FER_RGMII	<< 0;
-		rgmiifer |= RGMII_FER_RGMII	<< 4;
-		out_be32((void *)RGMII_FER, rgmiifer);
-		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
-		break;
-	case EMAC_PHY_MODE_NONE_GMII:
-		/* 1 x GMII port on channel 0 */
-		rgmiifer |= RGMII_FER_GMII	<< 0;
-		rgmiifer |= RGMII_FER_DIS	<< 4;
-		out_be32((void *)RGMII_FER, rgmiifer);
-		bis->bi_phymode[0] = BI_PHYMODE_GMII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		break;
-	case EMAC_PHY_MODE_NONE_MII:
-		/* 1 x MII port on channel 0 */
-		rgmiifer |= RGMII_FER_MII	<< 0;
-		rgmiifer |= RGMII_FER_DIS	<< 4;
-		out_be32((void *)RGMII_FER, rgmiifer);
-		bis->bi_phymode[0] = BI_PHYMODE_MII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		break;
-	case EMAC_PHY_MODE_GMII_NONE:
-		/* 1 x GMII port on channel 1 */
-		rgmiifer |= RGMII_FER_DIS	<< 0;
-		rgmiifer |= RGMII_FER_GMII	<< 4;
-		out_be32((void *)RGMII_FER, rgmiifer);
-		bis->bi_phymode[0] = BI_PHYMODE_NONE;
-		bis->bi_phymode[1] = BI_PHYMODE_GMII;
-		break;
-	case EMAC_PHY_MODE_MII_NONE:
-		/* 1 x MII port on channel 1 */
-		rgmiifer |= RGMII_FER_DIS	<< 0;
-		rgmiifer |= RGMII_FER_MII	<< 4;
-		out_be32((void *)RGMII_FER, rgmiifer);
-		bis->bi_phymode[0] = BI_PHYMODE_NONE;
-		bis->bi_phymode[1] = BI_PHYMODE_MII;
-		break;
-	default:
-		break;
-	}
-
-	/* Ensure we setup mdio for this devnum and ONLY this devnum */
-	rgmiifer = in_be32((void *)RGMII_FER);
-	rgmiifer |= (1 << (19-devnum));
-	out_be32((void *)RGMII_FER, rgmiifer);
-
-	return ((int)0x0);
-}
-#endif  /* CONFIG_405EX */
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
-{
-	u32 eth_cfg;
-	u32 zmiifer;		/* ZMII0_FER reg. */
-	u32 rmiifer;		/* RGMII0_FER reg. Bridge 0 */
-	u32 rmiifer1;		/* RGMII0_FER reg. Bridge 1 */
-	int mode;
-
-	zmiifer  = 0;
-	rmiifer  = 0;
-	rmiifer1 = 0;
-
-#if defined(CONFIG_460EX)
-	mode = 9;
-#else
-	mode = 10;
-#endif
-
-	/* TODO:
-	 * NOTE: 460GT has 2 RGMII bridge cores:
-	 *		emac0 ------ RGMII0_BASE
-	 *		           |
-	 *		emac1 -----+
-	 *
-	 *		emac2 ------ RGMII1_BASE
-	 *		           |
-	 *		emac3 -----+
-	 *
-	 *	460EX has 1 RGMII bridge core:
-	 *	and RGMII1_BASE is disabled
-	 *		emac0 ------ RGMII0_BASE
-	 *		           |
-	 *		emac1 -----+
-	 */
-
-	/*
-	 * Right now only 2*RGMII is supported. Please extend when needed.
-	 * sr - 2008-02-19
-	 */
-	switch (mode) {
-	case 1:
-		/* 1 MII - 460EX */
-		/* GMC0 EMAC4_0, ZMII Bridge */
-		zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
-		bis->bi_phymode[0] = BI_PHYMODE_MII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		bis->bi_phymode[2] = BI_PHYMODE_NONE;
-		bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		break;
-	case 2:
-		/* 2 MII - 460GT */
-		/* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
-		zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
-		bis->bi_phymode[0] = BI_PHYMODE_MII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		bis->bi_phymode[2] = BI_PHYMODE_MII;
-		bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		break;
-	case 3:
-		/* 2 RMII - 460EX */
-		/* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
-		bis->bi_phymode[0] = BI_PHYMODE_RMII;
-		bis->bi_phymode[1] = BI_PHYMODE_RMII;
-		bis->bi_phymode[2] = BI_PHYMODE_NONE;
-		bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		break;
-	case 4:
-		/* 4 RMII - 460GT */
-		/* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
-		/* ZMII Bridge */
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
-		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_RMII;
-		bis->bi_phymode[1] = BI_PHYMODE_RMII;
-		bis->bi_phymode[2] = BI_PHYMODE_RMII;
-		bis->bi_phymode[3] = BI_PHYMODE_RMII;
-		break;
-	case 5:
-		/* 2 SMII - 460EX */
-		/* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
-		bis->bi_phymode[0] = BI_PHYMODE_SMII;
-		bis->bi_phymode[1] = BI_PHYMODE_SMII;
-		bis->bi_phymode[2] = BI_PHYMODE_NONE;
-		bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		break;
-	case 6:
-		/* 4 SMII - 460GT */
-		/* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
-		/* ZMII Bridge */
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
-		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_SMII;
-		bis->bi_phymode[1] = BI_PHYMODE_SMII;
-		bis->bi_phymode[2] = BI_PHYMODE_SMII;
-		bis->bi_phymode[3] = BI_PHYMODE_SMII;
-		break;
-	case 7:
-		/* This is the default mode that we want for board bringup - Maple */
-		/* 1 GMII - 460EX */
-		/* GMC0 EMAC4_0, RGMII Bridge 0 */
-		rmiifer |= RGMII_FER_MDIO(0);
-
-		if (devnum == 0) {
-			rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
-			bis->bi_phymode[0] = BI_PHYMODE_GMII;
-			bis->bi_phymode[1] = BI_PHYMODE_NONE;
-			bis->bi_phymode[2] = BI_PHYMODE_NONE;
-			bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		} else {
-			rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
-			bis->bi_phymode[0] = BI_PHYMODE_NONE;
-			bis->bi_phymode[1] = BI_PHYMODE_GMII;
-			bis->bi_phymode[2] = BI_PHYMODE_NONE;
-			bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		}
-		break;
-	case 8:
-		/* 2 GMII - 460GT */
-		/* GMC0 EMAC4_0, RGMII Bridge 0 */
-		/* GMC1 EMAC4_2, RGMII Bridge 1 */
-		rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2);	/* CH0CFG - EMAC0 */
-		rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2);	/* CH0CFG - EMAC2 */
-		rmiifer |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC0 */
-		rmiifer1 |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC2 */
-
-		bis->bi_phymode[0] = BI_PHYMODE_GMII;
-		bis->bi_phymode[1] = BI_PHYMODE_NONE;
-		bis->bi_phymode[2] = BI_PHYMODE_GMII;
-		bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		break;
-	case 9:
-		/* 2 RGMII - 460EX */
-		/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
-		rmiifer |= RGMII_FER_MDIO(0);			/* enable MDIO - EMAC0 */
-
-		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[2] = BI_PHYMODE_NONE;
-		bis->bi_phymode[3] = BI_PHYMODE_NONE;
-		break;
-	case 10:
-		/* 4 RGMII - 460GT */
-		/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
-		/* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
-		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
-		rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
-		rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
-		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
-		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
-		break;
-	default:
-		break;
-	}
-
-	/* Set EMAC for MDIO */
-	mfsdr(SDR0_ETH_CFG, eth_cfg);
-	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
-	mtsdr(SDR0_ETH_CFG, eth_cfg);
-
-	out_be32((void *)RGMII_FER, rmiifer);
-#if defined(CONFIG_460GT)
-	out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
-#endif
-
-	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
-	mfsdr(SDR0_ETH_CFG, eth_cfg);
-	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
-	mtsdr(SDR0_ETH_CFG, eth_cfg);
-
-	return 0;
-}
-#endif /* CONFIG_460EX || CONFIG_460GT */
-
-static inline void *malloc_aligned(u32 size, u32 align)
-{
-	return (void *)(((u32)malloc(size + align) + align - 1) &
-			~(align - 1));
-}
-
-static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
-{
-	int i;
-	unsigned long reg = 0;
-	unsigned long msr;
-	unsigned long speed;
-	unsigned long duplex;
-	unsigned long failsafe;
-	unsigned mode_reg;
-	unsigned short devnum;
-	unsigned short reg_short;
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-	sys_info_t sysinfo;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-	int ethgroup = -1;
-#endif
-#endif
-	u32 bd_cached;
-	u32 bd_uncached = 0;
-#ifdef CONFIG_4xx_DCACHE
-	static u32 last_used_ea = 0;
-#endif
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-	int rgmii_channel;
-#endif
-
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	/* before doing anything, figure out if we have a MAC address */
-	/* if not, bail */
-	if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
-		printf("ERROR: ethaddr not set!\n");
-		return -1;
-	}
-
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-	/* Need to get the OPB frequency so we can access the PHY */
-	get_sys_info (&sysinfo);
-#endif
-
-	msr = mfmsr ();
-	mtmsr (msr & ~(MSR_EE));	/* disable interrupts */
-
-	devnum = hw_p->devnum;
-
-#ifdef INFO_4XX_ENET
-	/* AS.HARNOIS
-	 * We should have :
-	 * hw_p->stats.pkts_handled <=	hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
-	 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
-	 * is possible that new packets (without relationship with
-	 * current transfer) have got the time to arrived before
-	 * netloop calls eth_halt
-	 */
-	printf ("About preceeding transfer (eth%d):\n"
-		"- Sent packet number %d\n"
-		"- Received packet number %d\n"
-		"- Handled packet number %d\n",
-		hw_p->devnum,
-		hw_p->stats.pkts_tx,
-		hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
-
-	hw_p->stats.pkts_tx = 0;
-	hw_p->stats.pkts_rx = 0;
-	hw_p->stats.pkts_handled = 0;
-	hw_p->print_speed = 1;	/* print speed message again next time */
-#endif
-
-	hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
-	hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
-
-	hw_p->rx_slot = 0;	/* MAL Receive Slot */
-	hw_p->rx_i_index = 0;	/* Receive Interrupt Queue Index */
-	hw_p->rx_u_index = 0;	/* Receive User Queue Index */
-
-	hw_p->tx_slot = 0;	/* MAL Transmit Slot */
-	hw_p->tx_i_index = 0;	/* Transmit Interrupt Queue Index */
-	hw_p->tx_u_index = 0;	/* Transmit User Queue Index */
-
-#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
-	/* set RMII mode */
-	/* NOTE: 440GX spec states that mode is mutually exclusive */
-	/* NOTE: Therefore, disable all other EMACS, since we handle */
-	/* NOTE: only one emac at a time */
-	reg = 0;
-	out_be32((void *)ZMII_FER, 0);
-	udelay (100);
-
-#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-#elif defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
-#endif
-
-	out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
-#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-#if defined(CONFIG_405EX)
-	ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
-#endif
-
-	sync();
-
-	/* provide clocks for EMAC internal loopback  */
-	emac_loopback_enable(hw_p);
-
-	/* EMAC RESET */
-	out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-
-	/* remove clocks for EMAC internal loopback  */
-	emac_loopback_disable(hw_p);
-
-	failsafe = 1000;
-	while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
-		udelay (1000);
-		failsafe--;
-	}
-	if (failsafe <= 0)
-		printf("\nProblem resetting EMAC!\n");
-
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-	/* Whack the M1 register */
-	mode_reg = 0x0;
-	mode_reg &= ~0x00000038;
-	if (sysinfo.freqOPB <= 50000000);
-	else if (sysinfo.freqOPB <= 66666667)
-		mode_reg |= EMAC_M1_OBCI_66;
-	else if (sysinfo.freqOPB <= 83333333)
-		mode_reg |= EMAC_M1_OBCI_83;
-	else if (sysinfo.freqOPB <= 100000000)
-		mode_reg |= EMAC_M1_OBCI_100;
-	else
-		mode_reg |= EMAC_M1_OBCI_GT100;
-
-	out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
-#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-
-	/* wait for PHY to complete auto negotiation */
-	reg_short = 0;
-#ifndef CONFIG_CS8952_PHY
-	switch (devnum) {
-	case 0:
-		reg = CONFIG_PHY_ADDR;
-		break;
-#if defined (CONFIG_PHY1_ADDR)
-	case 1:
-		reg = CONFIG_PHY1_ADDR;
-		break;
-#endif
-#if defined (CONFIG_PHY2_ADDR)
-	case 2:
-		reg = CONFIG_PHY2_ADDR;
-		break;
-#endif
-#if defined (CONFIG_PHY3_ADDR)
-	case 3:
-		reg = CONFIG_PHY3_ADDR;
-		break;
-#endif
-	default:
-		reg = CONFIG_PHY_ADDR;
-		break;
-	}
-
-	bis->bi_phynum[devnum] = reg;
-
-#if defined(CONFIG_PHY_RESET)
-	/*
-	 * Reset the phy, only if its the first time through
-	 * otherwise, just check the speeds & feeds
-	 */
-	if (hw_p->first_init == 0) {
-#if defined(CONFIG_M88E1111_PHY)
-		miiphy_write (dev->name, reg, 0x14, 0x0ce3);
-		miiphy_write (dev->name, reg, 0x18, 0x4101);
-		miiphy_write (dev->name, reg, 0x09, 0x0e00);
-		miiphy_write (dev->name, reg, 0x04, 0x01e1);
-#endif
-		miiphy_reset (dev->name, reg);
-
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-
-#if defined(CONFIG_CIS8201_PHY)
-		/*
-		 * Cicada 8201 PHY needs to have an extended register whacked
-		 * for RGMII mode.
-		 */
-		if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
-#if defined(CONFIG_CIS8201_SHORT_ETCH)
-			miiphy_write (dev->name, reg, 23, 0x1300);
-#else
-			miiphy_write (dev->name, reg, 23, 0x1000);
-#endif
-			/*
-			 * Vitesse VSC8201/Cicada CIS8201 errata:
-			 * Interoperability problem with Intel 82547EI phys
-			 * This work around (provided by Vitesse) changes
-			 * the default timer convergence from 8ms to 12ms
-			 */
-			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
-			miiphy_write (dev->name, reg, 0x08, 0x0200);
-			miiphy_write (dev->name, reg, 0x1f, 0x52b5);
-			miiphy_write (dev->name, reg, 0x02, 0x0004);
-			miiphy_write (dev->name, reg, 0x01, 0x0671);
-			miiphy_write (dev->name, reg, 0x00, 0x8fae);
-			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
-			miiphy_write (dev->name, reg, 0x08, 0x0000);
-			miiphy_write (dev->name, reg, 0x1f, 0x0000);
-			/* end Vitesse/Cicada errata */
-		}
-#endif
-
-#if defined(CONFIG_ET1011C_PHY)
-		/*
-		 * Agere ET1011c PHY needs to have an extended register whacked
-		 * for RGMII mode.
-		 */
-		if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
-			miiphy_read (dev->name, reg, 0x16, &reg_short);
-			reg_short &= ~(0x7);
-			reg_short |= 0x6;	/* RGMII DLL Delay*/
-			miiphy_write (dev->name, reg, 0x16, reg_short);
-
-			miiphy_read (dev->name, reg, 0x17, &reg_short);
-			reg_short &= ~(0x40);
-			miiphy_write (dev->name, reg, 0x17, reg_short);
-
-			miiphy_write(dev->name, reg, 0x1c, 0x74f0);
-		}
-#endif
-
-#endif
-		/* Start/Restart autonegotiation */
-		phy_setup_aneg (dev->name, reg);
-		udelay (1000);
-	}
-#endif /* defined(CONFIG_PHY_RESET) */
-
-	miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
-
-	/*
-	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
-	 */
-	if ((reg_short & PHY_BMSR_AUTN_ABLE)
-	    && !(reg_short & PHY_BMSR_AUTN_COMP)) {
-		puts ("Waiting for PHY auto negotiation to complete");
-		i = 0;
-		while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
-			/*
-			 * Timeout reached ?
-			 */
-			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
-				puts (" TIMEOUT !\n");
-				break;
-			}
-
-			if ((i++ % 1000) == 0) {
-				putc ('.');
-			}
-			udelay (1000);	/* 1 ms */
-			miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
-
-		}
-		puts (" done\n");
-		udelay (500000);	/* another 500 ms (results in faster booting) */
-	}
-#endif /* #ifndef CONFIG_CS8952_PHY */
-
-	speed = miiphy_speed (dev->name, reg);
-	duplex = miiphy_duplex (dev->name, reg);
-
-	if (hw_p->print_speed) {
-		hw_p->print_speed = 0;
-		printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
-			(int) speed, (duplex == HALF) ? "HALF" : "FULL",
-			hw_p->devnum);
-	}
-
-#if defined(CONFIG_440) && \
-    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
-    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
-    !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	mfsdr(sdr_mfr, reg);
-	if (speed == 100) {
-		reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
-	} else {
-		reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
-	}
-	mtsdr(sdr_mfr, reg);
-#endif
-
-	/* Set ZMII/RGMII speed according to the phy link speed */
-	reg = in_be32((void *)ZMII_SSR);
-	if ( (speed == 100) || (speed == 1000) )
-		out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
-	else
-		out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
-
-	if ((devnum == 2) || (devnum == 3)) {
-		if (speed == 1000)
-			reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
-		else if (speed == 100)
-			reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
-		else if (speed == 10)
-			reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
-		else {
-			printf("Error in RGMII Speed\n");
-			return -1;
-		}
-		out_be32((void *)RGMII_SSR, reg);
-	}
-#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-	if (devnum >= 2)
-		rgmii_channel = devnum - 2;
-	else
-		rgmii_channel = devnum;
-
-	if (speed == 1000)
-		reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
-	else if (speed == 100)
-		reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
-	else if (speed == 10)
-		reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
-	else {
-		printf("Error in RGMII Speed\n");
-		return -1;
-	}
-	out_be32((void *)RGMII_SSR, reg);
-#if defined(CONFIG_460GT)
-	if ((devnum == 2) || (devnum == 3))
-		out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
-#endif
-#endif
-
-	/* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
-	       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
-#else
-	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
-	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
-	if (get_pvr() == PVR_440GP_RB) {
-		mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
-	}
-#endif
-
-	/*
-	 * Malloc MAL buffer desciptors, make sure they are
-	 * aligned on cache line boundary size
-	 * (401/403/IOP480 = 16, 405 = 32)
-	 * and doesn't cross cache block boundaries.
-	 */
-	if (hw_p->first_init == 0) {
-		debug("*** Allocating descriptor memory ***\n");
-
-		bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
-		if (!bd_cached) {
-			printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
-			return -1;
-		}
-
-#ifdef CONFIG_4xx_DCACHE
-		flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
-		if (!last_used_ea)
-#if defined(CFG_MEM_TOP_HIDE)
-			bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE;
-#else
-			bd_uncached = bis->bi_memsize;
-#endif
-		else
-			bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
-
-		last_used_ea = bd_uncached;
-		program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
-			    TLB_WORD2_I_ENABLE);
-#else
-		bd_uncached = bd_cached;
-#endif
-		hw_p->tx_phys = bd_cached;
-		hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
-		hw_p->tx = (mal_desc_t *)(bd_uncached);
-		hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
-		debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
-	}
-
-	for (i = 0; i < NUM_TX_BUFF; i++) {
-		hw_p->tx[i].ctrl = 0;
-		hw_p->tx[i].data_len = 0;
-		if (hw_p->first_init == 0)
-			hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
-							 L1_CACHE_BYTES);
-		hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
-		if ((NUM_TX_BUFF - 1) == i)
-			hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
-		hw_p->tx_run[i] = -1;
-		debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
-	}
-
-	for (i = 0; i < NUM_RX_BUFF; i++) {
-		hw_p->rx[i].ctrl = 0;
-		hw_p->rx[i].data_len = 0;
-		hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
-		if ((NUM_RX_BUFF - 1) == i)
-			hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
-		hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
-		hw_p->rx_ready[i] = -1;
-		debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
-	}
-
-	reg = 0x00000000;
-
-	reg |= dev->enetaddr[0];	/* set high address */
-	reg = reg << 8;
-	reg |= dev->enetaddr[1];
-
-	out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
-
-	reg = 0x00000000;
-	reg |= dev->enetaddr[2];	/* set low address  */
-	reg = reg << 8;
-	reg |= dev->enetaddr[3];
-	reg = reg << 8;
-	reg |= dev->enetaddr[4];
-	reg = reg << 8;
-	reg |= dev->enetaddr[5];
-
-	out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
-
-	switch (devnum) {
-	case 1:
-		/* setup MAL tx & rx channel pointers */
-#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
-		mtdcr (maltxctp2r, hw_p->tx_phys);
-#else
-		mtdcr (maltxctp1r, hw_p->tx_phys);
-#endif
-#if defined(CONFIG_440)
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (malrxbattr, 0x0);
-#endif
-
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-		mtdcr (malrxctp8r, hw_p->rx_phys);
-		/* set RX buffer size */
-		mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
-#else
-		mtdcr (malrxctp1r, hw_p->rx_phys);
-		/* set RX buffer size */
-		mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
-#endif
-		break;
-#if defined (CONFIG_440GX)
-	case 2:
-		/* setup MAL tx & rx channel pointers */
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (malrxbattr, 0x0);
-		mtdcr (maltxctp2r, hw_p->tx_phys);
-		mtdcr (malrxctp2r, hw_p->rx_phys);
-		/* set RX buffer size */
-		mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-	case 3:
-		/* setup MAL tx & rx channel pointers */
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (maltxctp3r, hw_p->tx_phys);
-		mtdcr (malrxbattr, 0x0);
-		mtdcr (malrxctp3r, hw_p->rx_phys);
-		/* set RX buffer size */
-		mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-#endif /* CONFIG_440GX */
-#if defined (CONFIG_460GT)
-	case 2:
-		/* setup MAL tx & rx channel pointers */
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (malrxbattr, 0x0);
-		mtdcr (maltxctp2r, hw_p->tx_phys);
-		mtdcr (malrxctp16r, hw_p->rx_phys);
-		/* set RX buffer size */
-		mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-	case 3:
-		/* setup MAL tx & rx channel pointers */
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (malrxbattr, 0x0);
-		mtdcr (maltxctp3r, hw_p->tx_phys);
-		mtdcr (malrxctp24r, hw_p->rx_phys);
-		/* set RX buffer size */
-		mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-#endif /* CONFIG_460GT */
-	case 0:
-	default:
-		/* setup MAL tx & rx channel pointers */
-#if defined(CONFIG_440)
-		mtdcr (maltxbattr, 0x0);
-		mtdcr (malrxbattr, 0x0);
-#endif
-		mtdcr (maltxctp0r, hw_p->tx_phys);
-		mtdcr (malrxctp0r, hw_p->rx_phys);
-		/* set RX buffer size */
-		mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
-		break;
-	}
-
-	/* Enable MAL transmit and receive channels */
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
-#else
-	mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
-#endif
-	mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
-
-	/* set transmit enable & receive enable */
-	out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
-
-	mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
-
-	/* set rx-/tx-fifo size */
-	mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
-
-	/* set speed */
-	if (speed == _1000BASET) {
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-		unsigned long pfc1;
-
-		mfsdr (sdr_pfc1, pfc1);
-		pfc1 |= SDR0_PFC1_EM_1000;
-		mtsdr (sdr_pfc1, pfc1);
-#endif
-		mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
-	} else if (speed == _100BASET)
-		mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
-	else
-		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
-	if (duplex == FULL)
-		mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
-
-	out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
-
-	/* Enable broadcast and indvidual address */
-	/* TBS: enabling runts as some misbehaved nics will send runts */
-	out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
-
-	/* we probably need to set the tx mode1 reg? maybe at tx time */
-
-	/* set transmit request threshold register */
-	out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000);	/* 256 byte threshold */
-
-	/* set receive	low/high water mark register */
-#if defined(CONFIG_440)
-	/* 440s has a 64 byte burst length */
-	out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
-#else
-	/* 405s have a 16 byte burst length */
-	out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
-#endif /* defined(CONFIG_440) */
-	out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
-
-	/* Set fifo limit entry in tx mode 0 */
-	out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
-	/* Frame gap set */
-	out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
-
-	/* Set EMAC IER */
-	hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
-	if (speed == _100BASET)
-		hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
-
-	out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff);	/* clear pending interrupts */
-	out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
-
-	if (hw_p->first_init == 0) {
-		/*
-		 * Connect interrupt service routines
-		 */
-		irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
-				    (interrupt_handler_t *) enetInt, dev);
-	}
-
-	mtmsr (msr);		/* enable interrupts again */
-
-	hw_p->bis = bis;
-	hw_p->first_init = 1;
-
-	return 0;
-}
-
-
-static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
-			      int len)
-{
-	struct enet_frame *ef_ptr;
-	ulong time_start, time_now;
-	unsigned long temp_txm0;
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	ef_ptr = (struct enet_frame *) ptr;
-
-	/*-----------------------------------------------------------------------+
-	 *  Copy in our address into the frame.
-	 *-----------------------------------------------------------------------*/
-	(void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
-
-	/*-----------------------------------------------------------------------+
-	 * If frame is too long or too short, modify length.
-	 *-----------------------------------------------------------------------*/
-	/* TBS: where does the fragment go???? */
-	if (len > ENET_MAX_MTU)
-		len = ENET_MAX_MTU;
-
-	/*   memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
-	memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
-	flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
-
-	/*-----------------------------------------------------------------------+
-	 * set TX Buffer busy, and send it
-	 *-----------------------------------------------------------------------*/
-	hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
-					EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
-		~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
-	if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
-		hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
-
-	hw_p->tx[hw_p->tx_slot].data_len = (short) len;
-	hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
-
-	sync();
-
-	out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
-		 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
-#ifdef INFO_4XX_ENET
-	hw_p->stats.pkts_tx++;
-#endif
-
-	/*-----------------------------------------------------------------------+
-	 * poll unitl the packet is sent and then make sure it is OK
-	 *-----------------------------------------------------------------------*/
-	time_start = get_timer (0);
-	while (1) {
-		temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
-		/* loop until either TINT turns on or 3 seconds elapse */
-		if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
-			/* transmit is done, so now check for errors
-			 * If there is an error, an interrupt should
-			 * happen when we return
-			 */
-			time_now = get_timer (0);
-			if ((time_now - time_start) > 3000) {
-				return (-1);
-			}
-		} else {
-			return (len);
-		}
-	}
-}
-
-int enetInt (struct eth_device *dev)
-{
-	int serviced;
-	int rc = -1;		/* default to not us */
-	u32 mal_isr;
-	u32 emac_isr = 0;
-	u32 mal_eob;
-	u32 uic_mal;
-	u32 uic_mal_err;
-	u32 uic_emac;
-	u32 uic_emac_b;
-	EMAC_4XX_HW_PST hw_p;
-
-	/*
-	 * Because the mal is generic, we need to get the current
-	 * eth device
-	 */
-#if defined(CONFIG_NET_MULTI)
-	dev = eth_get_dev();
-#else
-	dev = emac0_dev;
-#endif
-
-	hw_p = dev->priv;
-
-	/* enter loop that stays in interrupt code until nothing to service */
-	do {
-		serviced = 0;
-
-		uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
-		uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
-		uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
-		uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
-
-		if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
-		    && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
-		    && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
-			/* not for us */
-			return (rc);
-		}
-
-		/* get and clear controller status interrupts */
-		/* look at MAL and EMAC error interrupts */
-		if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
-			/* we have a MAL error interrupt */
-			mal_isr = mfdcr(malesr);
-			mal_err(dev, mal_isr, uic_mal_err,
-				 MAL_UIC_DEF, MAL_UIC_ERR);
-
-			/* clear MAL error interrupt status bits */
-			mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
-			      UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
-
-			return -1;
-		}
-
-		/* look for EMAC errors */
-		if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
-			emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
-			emac_err(dev, emac_isr);
-
-			/* clear EMAC error interrupt status bits */
-			mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
-			mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
-
-			return -1;
-		}
-
-		/* handle MAX TX EOB interrupt from a tx */
-		if (uic_mal & UIC_MAL_TXEOB) {
-			/* clear MAL interrupt status bits */
-			mal_eob = mfdcr(maltxeobisr);
-			mtdcr(maltxeobisr, mal_eob);
-			mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
-
-			/* indicate that we serviced an interrupt */
-			serviced = 1;
-			rc = 0;
-		}
-
-		/* handle MAL RX EOB interupt from a receive */
-		/* check for EOB on valid channels	     */
-		if (uic_mal & UIC_MAL_RXEOB) {
-			mal_eob = mfdcr(malrxeobisr);
-			if (mal_eob &
-			    (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
-				/* push packet to upper layer */
-				enet_rcv(dev, emac_isr);
-
-				/* clear MAL interrupt status bits */
-				mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
-
-				/* indicate that we serviced an interrupt */
-				serviced = 1;
-				rc = 0;
-			}
-		}
-	} while (serviced);
-
-	return (rc);
-}
-
-/*-----------------------------------------------------------------------------+
- *  MAL Error Routine
- *-----------------------------------------------------------------------------*/
-static void mal_err (struct eth_device *dev, unsigned long isr,
-		     unsigned long uic, unsigned long maldef,
-		     unsigned long mal_errr)
-{
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	mtdcr (malesr, isr);	/* clear interrupt */
-
-	/* clear DE interrupt */
-	mtdcr (maltxdeir, 0xC0000000);
-	mtdcr (malrxdeir, 0x80000000);
-
-#ifdef INFO_4XX_ENET
-	printf ("\nMAL error occured.... ISR = %lx UIC = = %lx	MAL_DEF = %lx  MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
-#endif
-
-	eth_init (hw_p->bis);	/* start again... */
-}
-
-/*-----------------------------------------------------------------------------+
- *  EMAC Error Routine
- *-----------------------------------------------------------------------------*/
-static void emac_err (struct eth_device *dev, unsigned long isr)
-{
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
-	out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
-}
-
-/*-----------------------------------------------------------------------------+
- *  enet_rcv() handles the ethernet receive data
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr)
-{
-	struct enet_frame *ef_ptr;
-	unsigned long data_len;
-	unsigned long rx_eob_isr;
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	int handled = 0;
-	int i;
-	int loop_count = 0;
-
-	rx_eob_isr = mfdcr (malrxeobisr);
-	if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
-		/* clear EOB */
-		mtdcr (malrxeobisr, rx_eob_isr);
-
-		/* EMAC RX done */
-		while (1) {	/* do all */
-			i = hw_p->rx_slot;
-
-			if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
-			    || (loop_count >= NUM_RX_BUFF))
-				break;
-
-			loop_count++;
-			handled++;
-			data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff;	/* Get len */
-			if (data_len) {
-				if (data_len > ENET_MAX_MTU)	/* Check len */
-					data_len = 0;
-				else {
-					if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) {	/* Check Errors */
-						data_len = 0;
-						hw_p->stats.rx_err_log[hw_p->
-								       rx_err_index]
-							= hw_p->rx[i].ctrl;
-						hw_p->rx_err_index++;
-						if (hw_p->rx_err_index ==
-						    MAX_ERR_LOG)
-							hw_p->rx_err_index =
-								0;
-					}	/* emac_erros */
-				}	/* data_len < max mtu */
-			}	/* if data_len */
-			if (!data_len) {	/* no data */
-				hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY;	/* Free Recv Buffer */
-
-				hw_p->stats.data_len_err++;	/* Error at Rx */
-			}
-
-			/* !data_len */
-			/* AS.HARNOIS */
-			/* Check if user has already eaten buffer */
-			/* if not => ERROR */
-			else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
-				if (hw_p->is_receiving)
-					printf ("ERROR : Receive buffers are full!\n");
-				break;
-			} else {
-				hw_p->stats.rx_frames++;
-				hw_p->stats.rx += data_len;
-				ef_ptr = (struct enet_frame *) hw_p->rx[i].
-					data_ptr;
-#ifdef INFO_4XX_ENET
-				hw_p->stats.pkts_rx++;
-#endif
-				/* AS.HARNOIS
-				 * use ring buffer
-				 */
-				hw_p->rx_ready[hw_p->rx_i_index] = i;
-				hw_p->rx_i_index++;
-				if (NUM_RX_BUFF == hw_p->rx_i_index)
-					hw_p->rx_i_index = 0;
-
-				hw_p->rx_slot++;
-				if (NUM_RX_BUFF == hw_p->rx_slot)
-					hw_p->rx_slot = 0;
-
-				/*  AS.HARNOIS
-				 * free receive buffer only when
-				 * buffer has been handled (eth_rx)
-				 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
-				 */
-			}	/* if data_len */
-		}		/* while */
-	}			/* if EMACK_RXCHL */
-}
-
-
-static int ppc_4xx_eth_rx (struct eth_device *dev)
-{
-	int length;
-	int user_index;
-	unsigned long msr;
-	EMAC_4XX_HW_PST hw_p = dev->priv;
-
-	hw_p->is_receiving = 1; /* tell driver */
-
-	for (;;) {
-		/* AS.HARNOIS
-		 * use ring buffer and
-		 * get index from rx buffer desciptor queue
-		 */
-		user_index = hw_p->rx_ready[hw_p->rx_u_index];
-		if (user_index == -1) {
-			length = -1;
-			break;	/* nothing received - leave for() loop */
-		}
-
-		msr = mfmsr ();
-		mtmsr (msr & ~(MSR_EE));
-
-		length = hw_p->rx[user_index].data_len & 0x0fff;
-
-		/* Pass the packet up to the protocol layers. */
-		/*	 NetReceive(NetRxPackets[rxIdx], length - 4); */
-		/*	 NetReceive(NetRxPackets[i], length); */
-		invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
-					(u32)hw_p->rx[user_index].data_ptr +
-					length - 4);
-		NetReceive (NetRxPackets[user_index], length - 4);
-		/* Free Recv Buffer */
-		hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
-		/* Free rx buffer descriptor queue */
-		hw_p->rx_ready[hw_p->rx_u_index] = -1;
-		hw_p->rx_u_index++;
-		if (NUM_RX_BUFF == hw_p->rx_u_index)
-			hw_p->rx_u_index = 0;
-
-#ifdef INFO_4XX_ENET
-		hw_p->stats.pkts_handled++;
-#endif
-
-		mtmsr (msr);	/* Enable IRQ's */
-	}
-
-	hw_p->is_receiving = 0; /* tell driver */
-
-	return length;
-}
-
-int ppc_4xx_eth_initialize (bd_t * bis)
-{
-	static int virgin = 0;
-	struct eth_device *dev;
-	int eth_num = 0;
-	EMAC_4XX_HW_PST hw = NULL;
-	u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
-	u32 hw_addr[4];
-	u32 mal_ier;
-
-#if defined(CONFIG_440GX)
-	unsigned long pfc1;
-
-	mfsdr (sdr_pfc1, pfc1);
-	pfc1 &= ~(0x01e00000);
-	pfc1 |= 0x01200000;
-	mtsdr (sdr_pfc1, pfc1);
-#endif
-
-	/* first clear all mac-addresses */
-	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
-		memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
-
-	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
-		switch (eth_num) {
-		default:		/* fall through */
-		case 0:
-			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
-			       bis->bi_enetaddr, 6);
-			hw_addr[eth_num] = 0x0;
-			break;
-#ifdef CONFIG_HAS_ETH1
-		case 1:
-			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
-			       bis->bi_enet1addr, 6);
-			hw_addr[eth_num] = 0x100;
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH2
-		case 2:
-			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
-			       bis->bi_enet2addr, 6);
-#if defined(CONFIG_460GT)
-			hw_addr[eth_num] = 0x300;
-#else
-			hw_addr[eth_num] = 0x400;
-#endif
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH3
-		case 3:
-			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
-			       bis->bi_enet3addr, 6);
-#if defined(CONFIG_460GT)
-			hw_addr[eth_num] = 0x400;
-#else
-			hw_addr[eth_num] = 0x600;
-#endif
-			break;
-#endif
-		}
-	}
-
-	/* set phy num and mode */
-	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
-	bis->bi_phymode[0] = 0;
-
-#if defined(CONFIG_PHY1_ADDR)
-	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
-	bis->bi_phymode[1] = 0;
-#endif
-#if defined(CONFIG_440GX)
-	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
-	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
-	bis->bi_phymode[2] = 2;
-	bis->bi_phymode[3] = 2;
-#endif
-
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_405EX)
-	ppc_4xx_eth_setup_bridge(0, bis);
-#endif
-
-	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
-		/*
-		 * See if we can actually bring up the interface,
-		 * otherwise, skip it
-		 */
-		if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
-			bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-			continue;
-		}
-
-		/* Allocate device structure */
-		dev = (struct eth_device *) malloc (sizeof (*dev));
-		if (dev == NULL) {
-			printf ("ppc_4xx_eth_initialize: "
-				"Cannot allocate eth_device %d\n", eth_num);
-			return (-1);
-		}
-		memset(dev, 0, sizeof(*dev));
-
-		/* Allocate our private use data */
-		hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
-		if (hw == NULL) {
-			printf ("ppc_4xx_eth_initialize: "
-				"Cannot allocate private hw data for eth_device %d",
-				eth_num);
-			free (dev);
-			return (-1);
-		}
-		memset(hw, 0, sizeof(*hw));
-
-		hw->hw_addr = hw_addr[eth_num];
-		memcpy (dev->enetaddr, ethaddr[eth_num], 6);
-		hw->devnum = eth_num;
-		hw->print_speed = 1;
-
-		sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
-		dev->priv = (void *) hw;
-		dev->init = ppc_4xx_eth_init;
-		dev->halt = ppc_4xx_eth_halt;
-		dev->send = ppc_4xx_eth_send;
-		dev->recv = ppc_4xx_eth_rx;
-
-		if (0 == virgin) {
-			/* set the MAL IER ??? names may change with new spec ??? */
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_405EX)
-			mal_ier =
-				MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
-				MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
-#else
-			mal_ier =
-				MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
-				MAL_IER_OPBE | MAL_IER_PLBE;
-#endif
-			mtdcr (malesr, 0xffffffff);	/* clear pending interrupts */
-			mtdcr (maltxdeir, 0xffffffff);	/* clear pending interrupts */
-			mtdcr (malrxdeir, 0xffffffff);	/* clear pending interrupts */
-			mtdcr (malier, mal_ier);
-
-			/* install MAL interrupt handler */
-			irq_install_handler (VECNUM_MAL_SERR,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			irq_install_handler (VECNUM_MAL_TXEOB,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			irq_install_handler (VECNUM_MAL_RXEOB,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			irq_install_handler (VECNUM_MAL_TXDE,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			irq_install_handler (VECNUM_MAL_RXDE,
-					     (interrupt_handler_t *) enetInt,
-					     dev);
-			virgin = 1;
-		}
-
-#if defined(CONFIG_NET_MULTI)
-		eth_register (dev);
-#else
-		emac0_dev = dev;
-#endif
-
-#if defined(CONFIG_NET_MULTI)
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-		miiphy_register (dev->name,
-				 emac4xx_miiphy_read, emac4xx_miiphy_write);
-#endif
-#endif
-	}			/* end for each supported device */
-
-	return 0;
-}
-
-#if !defined(CONFIG_NET_MULTI)
-void eth_halt (void) {
-	if (emac0_dev) {
-		ppc_4xx_eth_halt(emac0_dev);
-		free(emac0_dev);
-		emac0_dev = NULL;
-	}
-}
-
-int eth_init (bd_t *bis)
-{
-	ppc_4xx_eth_initialize(bis);
-	if (emac0_dev) {
-		return ppc_4xx_eth_init(emac0_dev, bis);
-	} else {
-		printf("ERROR: ethaddr not set!\n");
-		return -1;
-	}
-}
-
-int eth_send(volatile void *packet, int length)
-{
-	return (ppc_4xx_eth_send(emac0_dev, packet, length));
-}
-
-int eth_rx(void)
-{
-	return (ppc_4xx_eth_rx(emac0_dev));
-}
-
-int emac4xx_miiphy_initialize (bd_t * bis)
-{
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-	miiphy_register ("ppc_4xx_eth0",
-			 emac4xx_miiphy_read, emac4xx_miiphy_write);
-#endif
-
-	return 0;
-}
-#endif /* !defined(CONFIG_NET_MULTI) */
-
-#endif
diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
new file mode 100644
index 0000000..1e3e20d
--- /dev/null
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -0,0 +1,1233 @@
+/*
+ * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+ * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
+ * DDR2 controller (non Denali Core). Those currently are:
+ *
+ * 405:		405EX
+ * 440/460:	440SP/440SPe/460EX/460GT/460SX
+ *
+ * (C) Copyright 2008 Applied Micro Circuits Corporation
+ * Adam Graham  <agraham@amcc.com>
+ *
+ * (C) Copyright 2007-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * COPYRIGHT   AMCC   CORPORATION 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#undef DEBUG
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+
+/*
+ * Only compile the DDR auto-calibration code for NOR boot and
+ * not for NAND boot (NAND SPL and NAND U-Boot - NUB)
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+
+#define MAXBXCF			4
+#define SDRAM_RXBAS_SHIFT_1M	20
+
+#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
+#define NUMMEMTESTS		24
+#else
+#define NUMMEMTESTS		8
+#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
+#define NUMLOOPS		1	/* configure as you deem approporiate */
+#define NUMMEMWORDS		16
+
+/* Private Structure Definitions */
+
+struct autocal_regs {
+	u32 rffd;
+	u32 rqfd;
+};
+
+struct ddrautocal {
+	u32 rffd;
+	u32 rffd_min;
+	u32 rffd_max;
+	u32 rffd_size;
+	u32 rqfd;
+	u32 rqfd_size;
+	u32 rdcc;
+	u32 flags;
+};
+
+struct sdram_timing {
+	u32 wrdtr;
+	u32 clktr;
+};
+
+struct sdram_timing_clks {
+	u32 wrdtr;
+	u32 clktr;
+	u32 rdcc;
+	u32 flags;
+};
+
+struct autocal_clks {
+	struct sdram_timing_clks clocks;
+	struct ddrautocal	 autocal;
+};
+
+/*--------------------------------------------------------------------------+
+ * Prototypes
+ *--------------------------------------------------------------------------*/
+#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
+static u32 DQS_calibration_methodA(struct ddrautocal *);
+static u32 program_DQS_calibration_methodA(struct ddrautocal *);
+#else
+static u32 DQS_calibration_methodB(struct ddrautocal *);
+static u32 program_DQS_calibration_methodB(struct ddrautocal *);
+#endif
+static int short_mem_test(u32 *);
+
+/*
+ * To provide an interface for board specific config values in this common
+ * DDR setup code, we implement he "weak" default functions here. They return
+ * the default value back to the caller.
+ *
+ * Please see include/configs/yucca.h for an example fora board specific
+ * implementation.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+u32 __ddr_wrdtr(u32 default_val)
+{
+	return default_val;
+}
+u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
+
+u32 __ddr_clktr(u32 default_val)
+{
+	return default_val;
+}
+u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
+
+/*
+ * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
+ */
+void __spd_ddr_init_hang(void)
+{
+	hang();
+}
+void
+spd_ddr_init_hang(void) __attribute__((weak, alias("__spd_ddr_init_hang")));
+#endif /* defined(CONFIG_SPD_EEPROM) */
+
+ulong __ddr_scan_option(ulong default_val)
+{
+	return default_val;
+}
+ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
+
+static u32 *get_membase(int bxcr_num)
+{
+	ulong bxcf;
+	u32 *membase;
+
+#if defined(SDRAM_R0BAS)
+	/* BAS from Memory Queue rank reg. */
+	membase =
+	    (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
+	bxcf = 0;	/* just to satisfy the compiler */
+#else
+	/* BAS from SDRAM_MBxCF mem rank reg. */
+	mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+	membase = (u32 *)((bxcf & 0xfff80000) << 3);
+#endif
+
+	return membase;
+}
+
+static inline void ecc_clear_status_reg(void)
+{
+	mtsdram(SDRAM_ECCCR, 0xffffffff);
+#if defined(SDRAM_R0BAS)
+	mtdcr(SDRAM_ERRSTATLL, 0xffffffff);
+#endif
+}
+
+/*
+ * Reset and relock memory DLL after SDRAM_CLKTR change
+ */
+static inline void relock_memory_DLL(void)
+{
+	u32 reg;
+
+	mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
+
+	do {
+		mfsdram(SDRAM_MCSTAT, reg);
+	} while (!(reg & SDRAM_MCSTAT_MIC_COMP));
+
+	mfsdram(SDRAM_MCOPT2, reg);
+	mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
+}
+
+static int ecc_check_status_reg(void)
+{
+	u32 ecc_status;
+
+	/*
+	 * Compare suceeded, now check
+	 * if got ecc error. If got an
+	 * ecc error, then don't count
+	 * this as a passing value
+	 */
+	mfsdram(SDRAM_ECCCR, ecc_status);
+	if (ecc_status != 0x00000000) {
+		/* clear on error */
+		ecc_clear_status_reg();
+		/* ecc check failure */
+		return 0;
+	}
+	ecc_clear_status_reg();
+	sync();
+
+	return 1;
+}
+
+/* return 1 if passes, 0 if fail */
+static int short_mem_test(u32 *base_address)
+{
+	int i, j, l;
+	u32 ecc_mode = 0;
+
+	ulong test[NUMMEMTESTS][NUMMEMWORDS] = {
+	/* 0 */	{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
+	/* 1 */	{0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
+	/* 2 */	{0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
+	/* 3 */	{0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
+	/* 4 */	{0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
+	/* 5 */	{0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
+	/* 6 */	{0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
+	/* 7 */	{0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55},
+
+#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
+	/* 8 */	{0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff},
+	/* 9 */	{0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
+		 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
+		 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe,
+		 0xfffefffe, 0xfffefffe, 0xfffefffe, 0xfffefffe},
+	/* 10 */{0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
+		 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
+		 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd,
+		 0xfffdfffd, 0xfffdfffd, 0xfffdffff, 0xfffdfffd},
+	/* 11 */{0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
+		 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
+		 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc,
+		 0xfffcfffc, 0xfffcfffc, 0xfffcfffc, 0xfffcfffc},
+	/* 12 */{0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
+		 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
+		 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb,
+		 0xfffbfffb, 0xfffffffb, 0xfffffffb, 0xfffffffb},
+	/* 13 */{0xfffafffa, 0xfffafffa, 0xfffffffa, 0xfffafffa,
+		 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
+		 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa,
+		 0xfffafffa, 0xfffafffa, 0xfffafffa, 0xfffafffa},
+	/* 14 */{0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
+		 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
+		 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9,
+		 0xfff9fff9, 0xfff9fff9, 0xfff9fff9, 0xfff9fff9},
+	/* 15 */{0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
+		 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
+		 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8,
+		 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8},
+	/* 16 */{0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
+		 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
+		 0xfff7fff7, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7,
+		 0xfff7ffff, 0xfff7ffff, 0xfff7fff7, 0xfff7fff7},
+	/* 17 */{0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
+		 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
+		 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7,
+		 0xfff6fff5, 0xfff6ffff, 0xfff6fff6, 0xfff6fff7},
+	/* 18 */{0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
+		 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
+		 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5,
+		 0xfff5fff4, 0xfff5ffff, 0xfff5fff5, 0xfff5fff5},
+	/* 19 */{0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
+		 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
+		 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4,
+		 0xfff4fff3, 0xfff4ffff, 0xfff4fff4, 0xfff4fff4},
+	/* 20 */{0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
+		 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
+		 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3,
+		 0xfff3fff2, 0xfff3ffff, 0xfff3fff3, 0xfff3fff3},
+	/* 21 */{0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
+		 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
+		 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2,
+		 0xfff2ffff, 0xfff2ffff, 0xfff2fff2, 0xfff2fff2},
+	/* 22 */{0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
+		 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
+		 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1,
+		 0xfff1ffff, 0xfff1ffff, 0xfff1fff1, 0xfff1fff1},
+	/* 23 */{0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
+		 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
+		 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
+		 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0},
+#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
+								 };
+
+	mfsdram(SDRAM_MCOPT1, ecc_mode);
+	if ((ecc_mode & SDRAM_MCOPT1_MCHK_CHK_REP) ==
+						SDRAM_MCOPT1_MCHK_CHK_REP) {
+		ecc_clear_status_reg();
+		sync();
+		ecc_mode = 1;
+	} else {
+		ecc_mode = 0;
+	}
+
+	/*
+	 * Run the short memory test.
+	 */
+	for (i = 0; i < NUMMEMTESTS; i++) {
+		for (j = 0; j < NUMMEMWORDS; j++) {
+			base_address[j] = test[i][j];
+			ppcDcbf((ulong)&(base_address[j]));
+		}
+		sync();
+		for (l = 0; l < NUMLOOPS; l++) {
+			for (j = 0; j < NUMMEMWORDS; j++) {
+				if (base_address[j] != test[i][j]) {
+					ppcDcbf((u32)&(base_address[j]));
+					return 0;
+				} else {
+					if (ecc_mode) {
+						if (!ecc_check_status_reg())
+							return 0;
+					}
+				}
+				ppcDcbf((u32)&(base_address[j]));
+			} /* for (j = 0; j < NUMMEMWORDS; j++) */
+			sync();
+		} /* for (l=0; l<NUMLOOPS; l++) */
+	}
+
+	return 1;
+}
+
+#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
+/*-----------------------------------------------------------------------------+
+| program_DQS_calibration_methodA.
++-----------------------------------------------------------------------------*/
+static u32 program_DQS_calibration_methodA(struct ddrautocal *ddrcal)
+{
+	u32 pass_result = 0;
+
+#ifdef DEBUG
+	ulong temp;
+
+	mfsdram(SDRAM_RDCC, temp);
+	debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
+#endif
+
+	pass_result = DQS_calibration_methodA(ddrcal);
+
+	return pass_result;
+}
+
+/*
+ * DQS_calibration_methodA()
+ *
+ * Autocalibration Method A
+ *
+ *  ARRAY [Entire DQS Range] DQS_Valid_Window ;    initialized to all zeros
+ *  ARRAY [Entire FDBK Range] FDBK_Valid_Window;   initialized to all zeros
+ *  MEMWRITE(addr, expected_data);
+ *  for (i = 0; i < Entire DQS Range; i++) {       RQDC.RQFD
+ *      for (j = 0; j < Entire FDBK Range; j++) {  RFDC.RFFD
+ *         MEMREAD(addr, actual_data);
+ *         if (actual_data == expected_data) {
+ *             DQS_Valid_Window[i] = 1;            RQDC.RQFD
+ *             FDBK_Valid_Window[i][j] = 1;        RFDC.RFFD
+ *         }
+ *      }
+ *  }
+ */
+static u32 DQS_calibration_methodA(struct ddrautocal *cal)
+{
+	ulong rfdc_reg;
+	ulong rffd;
+
+	ulong rqdc_reg;
+	ulong rqfd;
+
+	u32 *membase;
+	ulong bxcf;
+	int rqfd_average;
+	int bxcr_num;
+	int rffd_average;
+	int pass;
+	u32 passed = 0;
+
+	int in_window;
+	struct autocal_regs curr_win_min;
+	struct autocal_regs curr_win_max;
+	struct autocal_regs best_win_min;
+	struct autocal_regs best_win_max;
+	struct autocal_regs loop_win_min;
+	struct autocal_regs loop_win_max;
+
+#ifdef DEBUG
+	ulong temp;
+#endif
+	ulong rdcc;
+
+	char slash[] = "\\|/-\\|/-";
+	int loopi = 0;
+
+	/* start */
+	in_window = 0;
+
+	memset(&curr_win_min, 0, sizeof(curr_win_min));
+	memset(&curr_win_max, 0, sizeof(curr_win_max));
+	memset(&best_win_min, 0, sizeof(best_win_min));
+	memset(&best_win_max, 0, sizeof(best_win_max));
+	memset(&loop_win_min, 0, sizeof(loop_win_min));
+	memset(&loop_win_max, 0, sizeof(loop_win_max));
+
+	rdcc = 0;
+
+	/*
+	 * Program RDCC register
+	 * Read sample cycle auto-update enable
+	 */
+	mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T1 | SDRAM_RDCC_RSAE_ENABLE);
+
+#ifdef DEBUG
+	mfsdram(SDRAM_RDCC, temp);
+	debug("<%s>SDRAM_RDCC=0x%x\n", __func__, temp);
+	mfsdram(SDRAM_RTSR, temp);
+	debug("<%s>SDRAM_RTSR=0x%x\n", __func__, temp);
+	mfsdram(SDRAM_FCSR, temp);
+	debug("<%s>SDRAM_FCSR=0x%x\n", __func__, temp);
+#endif
+
+	/*
+	 * Program RQDC register
+	 * Internal DQS delay mechanism enable
+	 */
+	mtsdram(SDRAM_RQDC,
+		SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x00));
+
+#ifdef DEBUG
+	mfsdram(SDRAM_RQDC, temp);
+	debug("<%s>SDRAM_RQDC=0x%x\n", __func__, temp);
+#endif
+
+	/*
+	 * Program RFDC register
+	 * Set Feedback Fractional Oversample
+	 * Auto-detect read sample cycle enable
+	 */
+	mtsdram(SDRAM_RFDC, SDRAM_RFDC_ARSE_ENABLE |
+		SDRAM_RFDC_RFOS_ENCODE(0) | SDRAM_RFDC_RFFD_ENCODE(0));
+
+#ifdef DEBUG
+	mfsdram(SDRAM_RFDC, temp);
+	debug("<%s>SDRAM_RFDC=0x%x\n", __func__, temp);
+#endif
+
+	putc(' ');
+	for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
+
+		mfsdram(SDRAM_RQDC, rqdc_reg);
+		rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
+		mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
+
+		putc('\b');
+		putc(slash[loopi++ % 8]);
+
+		curr_win_min.rffd = 0;
+		curr_win_max.rffd = 0;
+		in_window = 0;
+
+		for (rffd = 0, pass = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
+			mfsdram(SDRAM_RFDC, rfdc_reg);
+			rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
+			mtsdram(SDRAM_RFDC,
+				    rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
+
+			for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
+				mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+
+				/* Banks enabled */
+				if (bxcf & SDRAM_BXCF_M_BE_MASK) {
+					/* Bank is enabled */
+					membase = get_membase(bxcr_num);
+					pass = short_mem_test(membase);
+				} /* if bank enabled */
+			} /* for bxcr_num */
+
+			/* If this value passed update RFFD windows */
+			if (pass && !in_window) { /* at the start of window */
+				in_window = 1;
+				curr_win_min.rffd = curr_win_max.rffd = rffd;
+				curr_win_min.rqfd = curr_win_max.rqfd = rqfd;
+				mfsdram(SDRAM_RDCC, rdcc); /*record this value*/
+			} else if (!pass && in_window) { /* at end of window */
+				in_window = 0;
+			} else if (pass && in_window) { /* within the window */
+				curr_win_max.rffd = rffd;
+				curr_win_max.rqfd = rqfd;
+			}
+			/* else if (!pass && !in_window)
+				skip - no pass, not currently in a window */
+
+			if (in_window) {
+				if ((curr_win_max.rffd - curr_win_min.rffd) >
+				    (best_win_max.rffd - best_win_min.rffd)) {
+					best_win_min.rffd = curr_win_min.rffd;
+					best_win_max.rffd = curr_win_max.rffd;
+
+					best_win_min.rqfd = curr_win_min.rqfd;
+					best_win_max.rqfd = curr_win_max.rqfd;
+					cal->rdcc	  = rdcc;
+				}
+				passed = 1;
+			}
+		} /* RFDC.RFFD */
+
+		/*
+		 * save-off the best window results of the RFDC.RFFD
+		 * for this RQDC.RQFD setting
+		 */
+		/*
+		 * if (just ended RFDC.RFDC loop pass window) >
+		 *	(prior RFDC.RFFD loop pass window)
+		 */
+		if ((best_win_max.rffd - best_win_min.rffd) >
+		    (loop_win_max.rffd - loop_win_min.rffd)) {
+			loop_win_min.rffd = best_win_min.rffd;
+			loop_win_max.rffd = best_win_max.rffd;
+			loop_win_min.rqfd = rqfd;
+			loop_win_max.rqfd = rqfd;
+			debug("RQFD.min 0x%08x, RQFD.max 0x%08x, "
+			      "RFFD.min 0x%08x, RFFD.max 0x%08x\n",
+					loop_win_min.rqfd, loop_win_max.rqfd,
+					loop_win_min.rffd, loop_win_max.rffd);
+		}
+	} /* RQDC.RQFD */
+
+	putc('\b');
+
+	debug("\n");
+
+	if ((loop_win_min.rffd == 0) && (loop_win_max.rffd == 0) &&
+	    (best_win_min.rffd == 0) && (best_win_max.rffd == 0) &&
+	    (best_win_min.rqfd == 0) && (best_win_max.rqfd == 0)) {
+		passed = 0;
+	}
+
+	/*
+	 * Need to program RQDC before RFDC.
+	 */
+	debug("<%s> RQFD Min: 0x%x\n", __func__, loop_win_min.rqfd);
+	debug("<%s> RQFD Max: 0x%x\n", __func__, loop_win_max.rqfd);
+	rqfd_average = loop_win_max.rqfd;
+
+	if (rqfd_average < 0)
+		rqfd_average = 0;
+
+	if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
+		rqfd_average = SDRAM_RQDC_RQFD_MAX;
+
+	debug("<%s> RFFD average: 0x%08x\n", __func__, rqfd_average);
+	mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
+				SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
+
+	debug("<%s> RFFD Min: 0x%08x\n", __func__, loop_win_min.rffd);
+	debug("<%s> RFFD Max: 0x%08x\n", __func__, loop_win_max.rffd);
+	rffd_average = ((loop_win_min.rffd + loop_win_max.rffd) / 2);
+
+	if (rffd_average < 0)
+		rffd_average = 0;
+
+	if (rffd_average > SDRAM_RFDC_RFFD_MAX)
+		rffd_average = SDRAM_RFDC_RFFD_MAX;
+
+	debug("<%s> RFFD average: 0x%08x\n", __func__, rffd_average);
+	mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
+
+	/* if something passed, then return the size of the largest window */
+	if (passed != 0) {
+		passed		= loop_win_max.rffd - loop_win_min.rffd;
+		cal->rqfd	= rqfd_average;
+		cal->rffd	= rffd_average;
+		cal->rffd_min	= loop_win_min.rffd;
+		cal->rffd_max	= loop_win_max.rffd;
+	}
+
+	return (u32)passed;
+}
+
+#else	/* !defined(CONFIG_PPC4xx_DDR_METHOD_A) */
+
+/*-----------------------------------------------------------------------------+
+| program_DQS_calibration_methodB.
++-----------------------------------------------------------------------------*/
+static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal)
+{
+	u32 pass_result = 0;
+
+#ifdef DEBUG
+	ulong temp;
+#endif
+
+	/*
+	 * Program RDCC register
+	 * Read sample cycle auto-update enable
+	 */
+	mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T2 | SDRAM_RDCC_RSAE_ENABLE);
+
+#ifdef DEBUG
+	mfsdram(SDRAM_RDCC, temp);
+	debug("<%s>SDRAM_RDCC=0x%08x\n", __func__, temp);
+#endif
+
+	/*
+	 * Program RQDC register
+	 * Internal DQS delay mechanism enable
+	 */
+	mtsdram(SDRAM_RQDC,
+#if defined(CONFIG_DDR_RQDC_START_VAL)
+			SDRAM_RQDC_RQDE_ENABLE |
+			    SDRAM_RQDC_RQFD_ENCODE(CONFIG_DDR_RQDC_START_VAL));
+#else
+			SDRAM_RQDC_RQDE_ENABLE | SDRAM_RQDC_RQFD_ENCODE(0x38));
+#endif
+
+#ifdef DEBUG
+	mfsdram(SDRAM_RQDC, temp);
+	debug("<%s>SDRAM_RQDC=0x%08x\n", __func__, temp);
+#endif
+
+	/*
+	 * Program RFDC register
+	 * Set Feedback Fractional Oversample
+	 * Auto-detect read sample cycle enable
+	 */
+	mtsdram(SDRAM_RFDC,	SDRAM_RFDC_ARSE_ENABLE |
+				SDRAM_RFDC_RFOS_ENCODE(0) |
+				SDRAM_RFDC_RFFD_ENCODE(0));
+
+#ifdef DEBUG
+	mfsdram(SDRAM_RFDC, temp);
+	debug("<%s>SDRAM_RFDC=0x%08x\n", __func__, temp);
+#endif
+
+	pass_result = DQS_calibration_methodB(ddrcal);
+
+	return pass_result;
+}
+
+/*
+ * DQS_calibration_methodB()
+ *
+ * Autocalibration Method B
+ *
+ * ARRAY [Entire DQS Range] DQS_Valid_Window ;       initialized to all zeros
+ * ARRAY [Entire Feedback Range] FDBK_Valid_Window;  initialized to all zeros
+ * MEMWRITE(addr, expected_data);
+ * Initialialize the DQS delay to 80 degrees (MCIF0_RRQDC[RQFD]=0x38).
+ *
+ *  for (j = 0; j < Entire Feedback Range; j++) {
+ *      MEMREAD(addr, actual_data);
+ *       if (actual_data == expected_data) {
+ *           FDBK_Valid_Window[j] = 1;
+ *       }
+ * }
+ *
+ * Set MCIF0_RFDC[RFFD] to the middle of the FDBK_Valid_Window.
+ *
+ * for (i = 0; i < Entire DQS Range; i++) {
+ *     MEMREAD(addr, actual_data);
+ *     if (actual_data == expected_data) {
+ *         DQS_Valid_Window[i] = 1;
+ *      }
+ * }
+ *
+ * Set MCIF0_RRQDC[RQFD] to the middle of the DQS_Valid_Window.
+ */
+/*-----------------------------------------------------------------------------+
+| DQS_calibration_methodB.
++-----------------------------------------------------------------------------*/
+static u32 DQS_calibration_methodB(struct ddrautocal *cal)
+{
+	ulong rfdc_reg;
+	ulong rffd;
+
+	ulong rqdc_reg;
+	ulong rqfd;
+
+	ulong rdcc;
+
+	u32 *membase;
+	ulong bxcf;
+	int rqfd_average;
+	int bxcr_num;
+	int rffd_average;
+	int pass;
+	uint passed = 0;
+
+	int in_window;
+	u32 curr_win_min, curr_win_max;
+	u32 best_win_min, best_win_max;
+	u32 size = 0;
+
+	/*------------------------------------------------------------------
+	 | Test to determine the best read clock delay tuning bits.
+	 |
+	 | Before the DDR controller can be used, the read clock delay needs to
+	 | be set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
+	 | This value cannot be hardcoded into the program because it changes
+	 | depending on the board's setup and environment.
+	 | To do this, all delay values are tested to see if they
+	 | work or not.  By doing this, you get groups of fails with groups of
+	 | passing values.  The idea is to find the start and end of a passing
+	 | window and take the center of it to use as the read clock delay.
+	 |
+	 | A failure has to be seen first so that when we hit a pass, we know
+	 | that it is truely the start of the window.  If we get passing values
+	 | to start off with, we don't know if we are at the start of the window
+	 |
+	 | The code assumes that a failure will always be found.
+	 | If a failure is not found, there is no easy way to get the middle
+	 | of the passing window.  I guess we can pretty much pick any value
+	 | but some values will be better than others.  Since the lowest speed
+	 | we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
+	 | from experimentation it is safe to say you will always have a failure
+	 +-----------------------------------------------------------------*/
+
+	debug("\n\n");
+
+	in_window = 0;
+	rdcc = 0;
+
+	curr_win_min = curr_win_max = 0;
+	best_win_min = best_win_max = 0;
+	for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
+		mfsdram(SDRAM_RFDC, rfdc_reg);
+		rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
+		mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
+
+		pass = 1;
+		for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
+			mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+
+			/* Banks enabled */
+			if (bxcf & SDRAM_BXCF_M_BE_MASK) {
+				/* Bank is enabled */
+				membase = get_membase(bxcr_num);
+				pass &= short_mem_test(membase);
+			} /* if bank enabled */
+		} /* for bxcf_num */
+
+		/* If this value passed */
+		if (pass && !in_window) {	/* start of passing window */
+			in_window = 1;
+			curr_win_min = curr_win_max = rffd;
+			mfsdram(SDRAM_RDCC, rdcc);	/* record this value */
+		} else if (!pass && in_window) {	/* end passing window */
+			in_window = 0;
+		} else if (pass && in_window) {	/* within the passing window */
+			curr_win_max = rffd;
+		}
+
+		if (in_window) {
+			if ((curr_win_max - curr_win_min) >
+			    (best_win_max - best_win_min)) {
+				best_win_min = curr_win_min;
+				best_win_max = curr_win_max;
+				cal->rdcc    = rdcc;
+			}
+			passed = 1;
+		}
+	} /* for rffd */
+
+	if ((best_win_min == 0) && (best_win_max == 0))
+		passed = 0;
+	else
+		size = best_win_max - best_win_min;
+
+	debug("RFFD Min: 0x%x\n", best_win_min);
+	debug("RFFD Max: 0x%x\n", best_win_max);
+	rffd_average = ((best_win_min + best_win_max) / 2);
+
+	cal->rffd_min = best_win_min;
+	cal->rffd_max = best_win_max;
+
+	if (rffd_average < 0)
+		rffd_average = 0;
+
+	if (rffd_average > SDRAM_RFDC_RFFD_MAX)
+		rffd_average = SDRAM_RFDC_RFFD_MAX;
+
+	mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
+
+	rffd = rffd_average;
+	in_window = 0;
+
+	curr_win_min = curr_win_max = 0;
+	best_win_min = best_win_max = 0;
+	for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
+		mfsdram(SDRAM_RQDC, rqdc_reg);
+		rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
+		mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
+
+		pass = 1;
+		for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
+
+			mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+
+			/* Banks enabled */
+			if (bxcf & SDRAM_BXCF_M_BE_MASK) {
+				/* Bank is enabled */
+				membase = get_membase(bxcr_num);
+				pass &= short_mem_test(membase);
+			} /* if bank enabled */
+		} /* for bxcf_num */
+
+		/* If this value passed */
+		if (pass && !in_window) {
+			in_window = 1;
+			curr_win_min = curr_win_max = rqfd;
+		} else if (!pass && in_window) {
+			in_window = 0;
+		} else if (pass && in_window) {
+			curr_win_max = rqfd;
+		}
+
+		if (in_window) {
+			if ((curr_win_max - curr_win_min) >
+			    (best_win_max - best_win_min)) {
+				best_win_min = curr_win_min;
+				best_win_max = curr_win_max;
+			}
+			passed = 1;
+		}
+	} /* for rqfd */
+
+	if ((best_win_min == 0) && (best_win_max == 0))
+		passed = 0;
+
+	debug("RQFD Min: 0x%x\n", best_win_min);
+	debug("RQFD Max: 0x%x\n", best_win_max);
+	rqfd_average = ((best_win_min + best_win_max) / 2);
+
+	if (rqfd_average < 0)
+		rqfd_average = 0;
+
+	if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
+		rqfd_average = SDRAM_RQDC_RQFD_MAX;
+
+	mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
+					SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
+
+	mfsdram(SDRAM_RQDC, rqdc_reg);
+	mfsdram(SDRAM_RFDC, rfdc_reg);
+
+	/*
+	 * Need to program RQDC before RFDC. The value is read above.
+	 * That is the reason why auto cal not work.
+	 * See, comments below.
+	 */
+	mtsdram(SDRAM_RQDC, rqdc_reg);
+	mtsdram(SDRAM_RFDC, rfdc_reg);
+
+	debug("RQDC: 0x%08X\n", rqdc_reg);
+	debug("RFDC: 0x%08X\n", rfdc_reg);
+
+	/* if something passed, then return the size of the largest window */
+	if (passed != 0) {
+		passed		= size;
+		cal->rqfd	= rqfd_average;
+		cal->rffd	= rffd_average;
+	}
+
+	return (uint)passed;
+}
+#endif /* defined(CONFIG_PPC4xx_DDR_METHOD_A) */
+
+/*
+ * Default table for DDR auto-calibration of all
+ * possible WRDTR and CLKTR values.
+ * Table format is:
+ *	 {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]}
+ *
+ * Table is terminated with {-1, -1} value pair.
+ *
+ * Board vendors can specify their own board specific subset of
+ * known working {SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR]} value
+ * pairs via a board defined ddr_scan_option() function.
+ */
+struct sdram_timing full_scan_options[] = {
+	{0, 0}, {0, 1}, {0, 2}, {0, 3},
+	{1, 0}, {1, 1}, {1, 2}, {1, 3},
+	{2, 0}, {2, 1}, {2, 2}, {2, 3},
+	{3, 0}, {3, 1}, {3, 2}, {3, 3},
+	{4, 0}, {4, 1}, {4, 2}, {4, 3},
+	{5, 0}, {5, 1}, {5, 2}, {5, 3},
+	{6, 0}, {6, 1}, {6, 2}, {6, 3},
+	{-1, -1}
+};
+
+/*---------------------------------------------------------------------------+
+| DQS_calibration.
++----------------------------------------------------------------------------*/
+u32 DQS_autocalibration(void)
+{
+	u32 wdtr;
+	u32 clkp;
+	u32 result = 0;
+	u32 best_result = 0;
+	u32 best_rdcc;
+	struct ddrautocal ddrcal;
+	struct autocal_clks tcal;
+	ulong rfdc_reg;
+	ulong rqdc_reg;
+	u32 val;
+	int verbose_lvl = 0;
+	char *str;
+	char slash[] = "\\|/-\\|/-";
+	int loopi = 0;
+	struct sdram_timing *scan_list;
+
+#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
+	int i;
+	char tmp[64];	/* long enough for environment variables */
+#endif
+
+	memset(&tcal, 0, sizeof(tcal));
+
+	ddr_scan_option((ulong)full_scan_options);
+
+	scan_list =
+	      (struct sdram_timing *)ddr_scan_option((ulong)full_scan_options);
+
+	mfsdram(SDRAM_MCOPT1, val);
+	if ((val & SDRAM_MCOPT1_MCHK_CHK_REP) == SDRAM_MCOPT1_MCHK_CHK_REP)
+		str = "ECC Auto calibration -";
+	else
+		str = "Auto calibration -";
+
+	puts(str);
+
+#if defined(DEBUG_PPC4xx_DDR_AUTOCALIBRATION)
+	i = getenv_r("autocalib", tmp, sizeof(tmp));
+	if (i < 0)
+		strcpy(tmp, CONFIG_AUTOCALIB);
+
+	if (strcmp(tmp, "final") == 0) {
+		/* display the final autocalibration results only */
+		verbose_lvl = 1;
+	} else if (strcmp(tmp, "loop") == 0) {
+		/* display summary autocalibration info per iteration */
+		verbose_lvl = 2;
+	} else if (strcmp(tmp, "display") == 0) {
+		/* display full debug autocalibration window info. */
+		verbose_lvl = 3;
+	}
+#endif /* (DEBUG_PPC4xx_DDR_AUTOCALIBRATION) */
+
+	best_rdcc = (SDRAM_RDCC_RDSS_T4 >> 30);
+
+	while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) {
+		wdtr = scan_list->wrdtr;
+		clkp = scan_list->clktr;
+
+		mfsdram(SDRAM_WRDTR, val);
+		val &= ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK);
+		mtsdram(SDRAM_WRDTR, (val |
+			ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | (wdtr << 25))));
+
+		mtsdram(SDRAM_CLKTR, clkp << 30);
+
+		relock_memory_DLL();
+
+		putc('\b');
+		putc(slash[loopi++ % 8]);
+
+#ifdef DEBUG
+		debug("\n");
+		debug("*** --------------\n");
+		mfsdram(SDRAM_WRDTR, val);
+		debug("*** SDRAM_WRDTR set to 0x%08x\n", val);
+		mfsdram(SDRAM_CLKTR, val);
+		debug("*** SDRAM_CLKTR set to 0x%08x\n", val);
+#endif
+
+		debug("\n");
+		if (verbose_lvl > 2) {
+			printf("*** SDRAM_WRDTR (wdtr) set to %d\n", wdtr);
+			printf("*** SDRAM_CLKTR (clkp) set to %d\n", clkp);
+		}
+
+		memset(&ddrcal, 0, sizeof(ddrcal));
+
+		/*
+		 * DQS calibration.
+		 */
+		/*
+		 * program_DQS_calibration_method[A|B]() returns 0 if no
+		 * passing RFDC.[RFFD] window is found or returns the size
+		 * of the best passing window; in the case of a found passing
+		 * window, the ddrcal will contain the values of the best
+		 * window RQDC.[RQFD] and RFDC.[RFFD].
+		 */
+
+		/*
+		 * Call PPC4xx SDRAM DDR autocalibration methodA or methodB.
+		 * Default is methodB.
+		 * Defined the autocalibration method in the board specific
+		 * header file.
+		 * Please see include/configs/kilauea.h for an example for
+		 * a board specific implementation.
+		 */
+#if defined(CONFIG_PPC4xx_DDR_METHOD_A)
+		result = program_DQS_calibration_methodA(&ddrcal);
+#else
+		result = program_DQS_calibration_methodB(&ddrcal);
+#endif
+
+		sync();
+
+		/*
+		 * Clear potential errors resulting from auto-calibration.
+		 * If not done, then we could get an interrupt later on when
+		 * exceptions are enabled.
+		 */
+		set_mcsr(get_mcsr());
+
+		val = ddrcal.rdcc;	/* RDCC from the best passing window */
+
+		udelay(100);
+
+		if (verbose_lvl > 1) {
+			char *tstr;
+			switch ((val >> 30)) {
+			case 0:
+				if (result != 0)
+					tstr = "T1";
+				else
+					tstr = "N/A";
+				break;
+			case 1:
+				tstr = "T2";
+				break;
+			case 2:
+				tstr = "T3";
+				break;
+			case 3:
+				tstr = "T4";
+				break;
+			default:
+				tstr = "unknown";
+				break;
+			}
+			printf("** WRDTR(%d) CLKTR(%d), Wind (%d), best (%d), "
+			       "max-min(0x%04x)(0x%04x), RDCC: %s\n",
+				wdtr, clkp, result, best_result,
+				ddrcal.rffd_min, ddrcal.rffd_max, tstr);
+		}
+
+		/*
+		 * The DQS calibration "result" is either "0"
+		 * if no passing window was found, or is the
+		 * size of the RFFD passing window.
+		 */
+		if (result != 0) {
+			tcal.autocal.flags = 1;
+			debug("*** (%d)(%d) result passed window size: 0x%08x, "
+			      "rqfd = 0x%08x, rffd = 0x%08x, rdcc = 0x%08x\n",
+				wdtr, clkp, result, ddrcal.rqfd,
+				ddrcal.rffd, ddrcal.rdcc);
+			/*
+			 * Save the SDRAM_WRDTR and SDRAM_CLKTR
+			 * settings for the largest returned
+			 * RFFD passing window size.
+			 */
+			if (result > best_result) {
+				/*
+				 * want the lowest Read Sample Cycle Select
+				 */
+				val = (val & SDRAM_RDCC_RDSS_MASK) >> 30;
+				debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
+							val, best_rdcc);
+				if (val <= best_rdcc) {
+					best_rdcc = val;
+					tcal.clocks.wrdtr = wdtr;
+					tcal.clocks.clktr = clkp;
+					tcal.clocks.rdcc = (val << 30);
+					tcal.autocal.rqfd = ddrcal.rqfd;
+					tcal.autocal.rffd = ddrcal.rffd;
+					best_result = result;
+
+					if (verbose_lvl > 2) {
+						printf("** (%d)(%d)  "
+						       "best result: 0x%04x\n",
+							wdtr, clkp,
+							best_result);
+						printf("** (%d)(%d)  "
+						       "best WRDTR: 0x%04x\n",
+							wdtr, clkp,
+							tcal.clocks.wrdtr);
+						printf("** (%d)(%d)  "
+						       "best CLKTR: 0x%04x\n",
+							wdtr, clkp,
+							tcal.clocks.clktr);
+						printf("** (%d)(%d)  "
+						       "best RQDC: 0x%04x\n",
+							wdtr, clkp,
+							tcal.autocal.rqfd);
+						printf("** (%d)(%d)  "
+						       "best RFDC: 0x%04x\n",
+							wdtr, clkp,
+							tcal.autocal.rffd);
+						printf("** (%d)(%d)  "
+						       "best RDCC: 0x%08x\n",
+							wdtr, clkp,
+							(u32)tcal.clocks.rdcc);
+						mfsdram(SDRAM_RTSR, val);
+						printf("** (%d)(%d)  best "
+						       "loop RTSR: 0x%08x\n",
+							wdtr, clkp, val);
+						mfsdram(SDRAM_FCSR, val);
+						printf("** (%d)(%d)  best "
+						       "loop FCSR: 0x%08x\n",
+							wdtr, clkp, val);
+					}
+				} /* if (val <= best_rdcc) */
+			} /* if (result >= best_result) */
+		} /* if (result != 0) */
+		scan_list++;
+	} /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
+
+	if (tcal.autocal.flags == 1) {
+		if (verbose_lvl > 0) {
+			printf("*** --------------\n");
+			printf("*** best_result window size: %d\n",
+							best_result);
+			printf("*** best_result WRDTR: 0x%04x\n",
+							tcal.clocks.wrdtr);
+			printf("*** best_result CLKTR: 0x%04x\n",
+							tcal.clocks.clktr);
+			printf("*** best_result RQFD: 0x%04x\n",
+							tcal.autocal.rqfd);
+			printf("*** best_result RFFD: 0x%04x\n",
+							tcal.autocal.rffd);
+			printf("*** best_result RDCC: 0x%04x\n",
+							tcal.clocks.rdcc);
+			printf("*** --------------\n");
+			printf("\n");
+		}
+
+		/*
+		 * if got best passing result window, then lock in the
+		 * best CLKTR, WRDTR, RQFD, and RFFD values
+		 */
+		mfsdram(SDRAM_WRDTR, val);
+		mtsdram(SDRAM_WRDTR, (val &
+		    ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
+		    ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC |
+					(tcal.clocks.wrdtr << 25)));
+
+		mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
+
+		relock_memory_DLL();
+
+		mfsdram(SDRAM_RQDC, rqdc_reg);
+		rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
+		mtsdram(SDRAM_RQDC, rqdc_reg |
+				SDRAM_RQDC_RQFD_ENCODE(tcal.autocal.rqfd));
+
+		mfsdram(SDRAM_RQDC, rqdc_reg);
+		debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
+				rqdc_reg);
+
+		mfsdram(SDRAM_RFDC, rfdc_reg);
+		rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
+		mtsdram(SDRAM_RFDC, rfdc_reg |
+				SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
+
+		mfsdram(SDRAM_RFDC, rfdc_reg);
+		debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",
+				rfdc_reg);
+		mfsdram(SDRAM_RDCC, val);
+		debug("***  SDRAM_RDCC 0x%08x\n", val);
+	} else {
+		/*
+		 * no valid windows were found
+		 */
+		printf("DQS memory calibration window can not be determined, "
+		       "terminating u-boot.\n");
+		ppc4xx_ibm_ddr2_register_dump();
+		spd_ddr_init_hang();
+	}
+
+	blank_string(strlen(str));
+
+	return 0;
+}
+#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
+u32 DQS_autocalibration(void)
+{
+	return 0;
+}
+#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
+#endif /* defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index c28c7ac..e8871fc 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -108,12 +108,12 @@ void pci_405gp_init(struct pci_controller *hose)
 	bd_t *bd = gd->bd;
 
 	unsigned short temp_short;
-	unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
+	unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
 	char *ptmla_str, *ptmms_str;
 #endif
-	unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
-	unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
+	unsigned long ptmla[2]    = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
+	unsigned long ptmms[2]    = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
 	unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
 	unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
@@ -268,25 +268,25 @@ void pci_405gp_init(struct pci_controller *hose)
 	/*
 	 * Insert Subsystem Vendor and Device ID
 	 */
-	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 #ifdef CONFIG_CPCI405
 	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
-		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 	else
-		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
+		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
 #else
-	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 #endif
 
 	/*
 	 * Insert Class-code
 	 */
-#ifdef CFG_PCI_CLASSCODE
-	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
-#endif /* CFG_PCI_CLASSCODE */
+#ifdef CONFIG_SYS_PCI_CLASSCODE
+	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
+#endif /* CONFIG_SYS_PCI_CLASSCODE */
 
 	/*--------------------------------------------------------------------------+
-	 * If PCI speed = 66Mhz, set 66Mhz capable bit.
+	 * If PCI speed = 66MHz, set 66MHz capable bit.
 	 *--------------------------------------------------------------------------*/
 	if (bd->bi_pci_busfreq >= 66000000) {
 		pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
@@ -405,8 +405,8 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
  */
 static struct pci_config_table pci_405gp_config_table[] = {
 /*if VendID is 0 it terminates the table search (ie Walnut)*/
-#ifdef CFG_PCI_SUBSYS_VENDORID
-	{CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
+#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
+	{CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 #endif
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
@@ -488,10 +488,10 @@ int pci_440_init (struct pci_controller *hose)
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + reg_num++,
-		       CFG_PCI_TARGBASE,
-		       CFG_PCI_MEMBASE,
-#ifdef CFG_PCI_MEMSIZE
-		       CFG_PCI_MEMSIZE,
+		       CONFIG_SYS_PCI_TARGBASE,
+		       CONFIG_SYS_PCI_MEMBASE,
+#ifdef CONFIG_SYS_PCI_MEMSIZE
+		       CONFIG_SYS_PCI_MEMSIZE,
 #else
 		       0x10000000,
 #endif
@@ -523,11 +523,11 @@ int pci_440_init (struct pci_controller *hose)
 	/*--------------------------------------------------------------------------+
 	 * PCI target init
 	 *--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_SYS_PCI_TARGET_INIT)
 	pci_target_init(hose);                /* Let board setup pci target */
 #else
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
 	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
@@ -542,9 +542,9 @@ int pci_440_init (struct pci_controller *hose)
 
 	/*--------------------------------------------------------------------------+
 	 * PCI master init: default is one 256MB region for PCI memory:
-	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CFG_PCI_MEMBASE
+	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CONFIG_SYS_PCI_MEMBASE
 	 *--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_SYS_PCI_MASTER_INIT)
 	pci_master_init(hose);          /* Let board setup pci master */
 #else
 	out32r( PCIX0_POM0SA, 0 ); /* disable */
@@ -558,7 +558,7 @@ int pci_440_init (struct pci_controller *hose)
 	out32r( PCIX0_POM0LAL, 0x00000000 );
 	out32r( PCIX0_POM0LAH, 0x00000003 );
 #endif
-	out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
+	out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
 	out32r( PCIX0_POM0PCIAH, 0x00000000 );
 	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
 	out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 0aadc06..fd40d8a 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -49,12 +49,12 @@ enum {
 
 static int validate_endpoint(struct pci_controller *hose)
 {
-	if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
+	if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
 		return (is_end_point(0));
-	else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
+	else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
 		return (is_end_point(1));
-#if CFG_PCIE_NR_PORTS > 2
-	else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
+	else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
 		return (is_end_point(2));
 #endif
 
@@ -67,13 +67,13 @@ static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
 
 	/* use local configuration space for the first bus */
 	if (PCI_BUS(devfn) == 0) {
-		if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
-			base = (u8*)CFG_PCIE0_XCFGBASE;
-		if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
-			base = (u8*)CFG_PCIE1_XCFGBASE;
-#if CFG_PCIE_NR_PORTS > 2
-		if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
-			base = (u8*)CFG_PCIE2_XCFGBASE;
+		if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
+			base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
+		if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
+			base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
+		if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
+			base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
 #endif
 	}
 
@@ -86,7 +86,7 @@ static void pcie_dmer_disable(void)
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
 	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
 #endif
@@ -98,7 +98,7 @@ static void pcie_dmer_enable(void)
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
 	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
 #endif
@@ -286,7 +286,7 @@ static void ppc4xx_setup_utl(u32 port) {
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
 		break;
 	}
-	utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+	utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
 
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
@@ -412,21 +412,21 @@ static void ppc4xx_setup_utl(u32 port)
 	 */
 	switch (port) {
 	case 0:
-		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE));
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
 		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);	/* BAM 11100000=4KB */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
 		break;
 
 	case 1:
-		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE)
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
 			+ 0x1000);
 		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);	/* BAM 11100000=4KB */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
 		break;
 	}
-	utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+	utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
 
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
@@ -512,20 +512,20 @@ static void ppc4xx_setup_utl(u32 port)
 	switch (port) {
 	case 0:
 		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
 		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
 		break;
 
 	case 1:
 		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
 		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
 
 		break;
 	}
-	utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
+	utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
 
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
@@ -761,9 +761,9 @@ static inline u64 ppc4xx_get_cfgaddr(int port)
 {
 #if defined(CONFIG_405EX)
 	if (port == 0)
-		return (u64)CFG_PCIE0_CFGBASE;
+		return (u64)CONFIG_SYS_PCIE0_CFGBASE;
 	else
-		return (u64)CFG_PCIE1_CFGBASE;
+		return (u64)CONFIG_SYS_PCIE1_CFGBASE;
 #endif
 #if defined(CONFIG_440SPE)
 	if (ppc440spe_revB()) {
@@ -895,7 +895,7 @@ int ppc4xx_init_pcie_port(int port, int rootport)
 		mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
 		mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
 		break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
 		mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
 		mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
@@ -947,20 +947,20 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 
 	switch (port) {
 	case 0:
-		mbase = (u32 *)CFG_PCIE0_XCFGBASE;
-		rmbase = (u32 *)CFG_PCIE0_CFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
+		rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
 		break;
 	case 1:
-		mbase = (u32 *)CFG_PCIE1_XCFGBASE;
-		rmbase = (u32 *)CFG_PCIE1_CFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
+		rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
 		break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
-		mbase = (u32 *)CFG_PCIE2_XCFGBASE;
-		rmbase = (u32 *)CFG_PCIE2_CFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
+		rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
 		break;
 #endif
 	}
@@ -979,19 +979,19 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 	 * subregions and to enable the outbound translation.
 	 */
 	out_le32(mbase + PECFG_POM0LAH, 0x00000000);
-	out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
-		 port * CFG_PCIE_MEMSIZE);
+	out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
+		 port * CONFIG_SYS_PCIE_MEMSIZE);
 	debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
 	      in_le32(mbase + PECFG_POM0LAL));
 
 	switch (port) {
 	case 0:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
 		      mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
 		      mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
@@ -999,26 +999,26 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 		      mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
 		break;
 	case 1:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
 		      mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
 		      mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
 		      mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
 		      mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
 		break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
 		      mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
 		      mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
@@ -1072,17 +1072,17 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 
 	switch (port) {
 	case 0:
-		mbase = (u32 *)CFG_PCIE0_XCFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
 		break;
 	case 1:
-		mbase = (u32 *)CFG_PCIE1_XCFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
 		break;
-#if defined(CFG_PCIE2_CFGBASE)
+#if defined(CONFIG_SYS_PCIE2_CFGBASE)
 	case 2:
-		mbase = (u32 *)CFG_PCIE2_XCFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
 		break;
 #endif
 	}
@@ -1098,29 +1098,29 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 
 	switch (port) {
 	case 0:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		break;
 	case 1:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		break;
 #endif
 	}
@@ -1141,8 +1141,8 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 	out_le32(mbase + PECFG_BAR2HMPA, 0);
 	out_le32(mbase + PECFG_BAR2LMPA, 0);
 
-	out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
-	out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
+	out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
+	out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
 	out_le32(mbase + PECFG_PIMEN, 0x1);
 
 	/* Enable I/O, Mem, and Busmaster cycles */
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index 766e586..c106ac2 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -66,20 +66,20 @@ DECLARE_GLOBAL_DATA_PTR;
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART0_BASE	(CFG_PERIPHERAL_BASE + 0x00000300)
-#define UART1_BASE	(CFG_PERIPHERAL_BASE + 0x00000400)
+#define UART0_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
+#define UART1_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
 #else
-#define UART0_BASE	(CFG_PERIPHERAL_BASE + 0x00000200)
-#define UART1_BASE	(CFG_PERIPHERAL_BASE + 0x00000300)
+#define UART0_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
+#define UART1_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
 #endif
 
 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE	(CFG_PERIPHERAL_BASE + 0x00000600)
+#define UART2_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
 #endif
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART2_BASE	(CFG_PERIPHERAL_BASE + 0x00000500)
-#define UART3_BASE	(CFG_PERIPHERAL_BASE + 0x00000600)
+#define UART2_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
+#define UART3_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
 #endif
 
 #if defined(CONFIG_440GP)
@@ -147,7 +147,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ACTING_UART1_BASE	UART1_BASE
 #endif
 
-#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
+#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 #error "External serial clock not supported on AMCC PPC405EP!"
 #endif
 
@@ -199,8 +199,8 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
 	/* Correct UART frequency in bd-info struct now that
 	 * the UART divisor is available
 	 */
-#ifdef CFG_EXT_SERIAL_CLOCK
-	gd->uart_clk = CFG_EXT_SERIAL_CLOCK;
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+	gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 #else
 	gd->uart_clk = sys_info.freqUART / udiv;
 #endif
@@ -218,7 +218,7 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
 }
 
 #if (defined(CONFIG_440) || defined(CONFIG_405EX)) &&	\
-    !defined(CFG_EXT_SERIAL_CLOCK)
+    !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 static void serial_divs (int baudrate, unsigned long *pudiv,
 			 unsigned short *pbdiv)
 {
@@ -315,7 +315,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
 	mtcpr(cprperd0, reg);
 	*pbdiv = div / udiv;
 }
-#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
+#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
 
 /*
  * Minimal serial functions needed to use one of the SMC ports
@@ -328,18 +328,18 @@ int serial_init_dev(unsigned long base)
 	unsigned long reg;
 	unsigned long udiv;
 	unsigned short bdiv;
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	unsigned long tmp;
 #endif
 
 	MFREG(UART0_SDR, reg);
 	reg &= ~CR0_MASK;
 
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
 	tmp  = gd->baudrate * 16;
-	bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+	bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
 #else
 	/* For 440, the cpu clock is on divider chain A, UART on divider
 	 * chain B ... so cpu clock is irrelevant. Get the "optimized"
@@ -384,11 +384,11 @@ int serial_init_dev (unsigned long base)
 	clk = tmp = 0;
 	mfsdr(UART0_SDR, reg);
 	reg &= ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
 	tmp  = gd->baudrate * 16;
-	bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+	bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
 #else
 	serial_divs(gd->baudrate, &udiv, &bdiv);
 #endif
@@ -411,7 +411,7 @@ int serial_init_dev (unsigned long base)
 #ifdef CONFIG_405EP
 	reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
 	clk = gd->cpu_clk;
-	tmp = CFG_BASE_BAUD * 16;
+	tmp = CONFIG_SYS_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
 	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 		udiv = UDIV_MAX;
@@ -420,16 +420,16 @@ int serial_init_dev (unsigned long base)
 	mtdcr (cpc0_ucr, reg);
 #else /* CONFIG_405EP */
 	reg = mfdcr(cntrl0) & ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
-	clk = CFG_EXT_SERIAL_CLOCK;
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 	udiv = 1;
 	reg |= CR0_EXTCLK_ENA;
 #else
 	clk = gd->cpu_clk;
-#ifdef CFG_405_UART_ERRATA_59
+#ifdef CONFIG_SYS_405_UART_ERRATA_59
 	udiv = 31;			/* Errata 59: stuck at 31 */
 #else
-	tmp = CFG_BASE_BAUD * 16;
+	tmp = CONFIG_SYS_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
 	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 		udiv = UDIV_MAX;
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index c773400..96ab5c6 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -35,6 +35,9 @@ SOBJS	+= kgdb.o
 COBJS	:= 40x_spd_sdram.o
 COBJS	+= 44x_spd_ddr.o
 COBJS	+= 44x_spd_ddr2.o
+ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+COBJS	+= 4xx_ibm_ddr2_autocalib.o
+endif
 COBJS	+= 4xx_pci.o
 COBJS	+= 4xx_pcie.o
 COBJS	+= bedbug_405.o
@@ -57,7 +60,6 @@ COBJS	+= usb.o
 COBJS	+= usb_ohci.o
 COBJS	+= usbdev.o
 ifndef CONFIG_XILINX_440
-COBJS	+= 4xx_enet.o
 COBJS	+= 4xx_uart.o
 COBJS	+= gpio.o
 COBJS	+= miiphy.o
diff --git a/cpu/ppc4xx/cache.S b/cpu/ppc4xx/cache.S
index ceb3ec0..269716f 100644
--- a/cpu/ppc4xx/cache.S
+++ b/cpu/ppc4xx/cache.S
@@ -143,8 +143,8 @@ _GLOBAL(flush_dcache)
 _GLOBAL(invalidate_dcache)
 	addi	r6,0,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
-	lis	r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha	/* TBS for large sized cache */
-	ori	r7,r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
+	lis	r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha	/* TBS for large sized cache */
+	ori	r7,r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
 					/* NOTE: dccci invalidates both */
 	mtctr	r7			/* ways in the D cache */
 ..dcloop:
diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c
index 8b2954c..a1696d3 100644
--- a/cpu/ppc4xx/commproc.c
+++ b/cpu/ppc4xx/commproc.c
@@ -30,10 +30,10 @@
 
 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 
-#if defined(CFG_POST_WORD_ADDR)
-# define _POST_ADDR	((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR))
-#elif defined(CFG_POST_ALT_WORD_ADDR)
-# define _POST_ADDR	(CFG_POST_ALT_WORD_ADDR)
+#if defined(CONFIG_SYS_POST_WORD_ADDR)
+# define _POST_ADDR	((CONFIG_SYS_OCM_DATA_ADDR) + (CONFIG_SYS_POST_WORD_ADDR))
+#elif defined(CONFIG_SYS_POST_ALT_WORD_ADDR)
+# define _POST_ADDR	(CONFIG_SYS_POST_ALT_WORD_ADDR)
 #endif
 
 void post_word_store (ulong a)
@@ -57,7 +57,7 @@ ulong post_word_load (void)
 void bootcount_store (ulong a)
 {
 	volatile ulong *save_addr =
-		(volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR);
+		(volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
 
 	save_addr[0] = a;
 	save_addr[1] = BOOTCOUNT_MAGIC;
@@ -66,7 +66,7 @@ void bootcount_store (ulong a)
 ulong bootcount_load (void)
 {
 	volatile ulong *save_addr =
-		(volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR);
+		(volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
 
 	if (save_addr[1] != BOOTCOUNT_MAGIC)
 		return 0;
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index bc9335a..d09c4c2 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -36,11 +36,24 @@
 #include <command.h>
 #include <asm/cache.h>
 #include <ppc4xx.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 void board_reset(void);
 
+/*
+ * To provide an interface to detect CPU number for boards that support
+ * more then one CPU, we implement the "weak" default functions here.
+ *
+ * Returns CPU number
+ */
+int __get_cpu_num(void)
+{
+	return NA_OR_UNKNOWN_CPU;
+}
+int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
+
 #if defined(CONFIG_405GP) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -274,8 +287,13 @@ int checkcpu (void)
 #if !defined(CONFIG_IOP480)
 	char addstr[64] = "";
 	sys_info_t sys_info;
+	int cpu_num;
 
-	puts ("CPU:   ");
+	cpu_num = get_cpu_num();
+	if (cpu_num >= 0)
+		printf("CPU%d:  ", cpu_num);
+	else
+		puts("CPU:   ");
 
 	get_sys_info(&sys_info);
 
@@ -629,14 +647,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_BOARD_RESET)
 	board_reset();
 #else
-#if defined(CFG_4xx_RESET_TYPE)
-	mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
+#if defined(CONFIG_SYS_4xx_RESET_TYPE)
+	mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
 #else
 	/*
 	 * Initiate system reset in debug control register DBCR
 	 */
 	mtspr(dbcr0, 0x30000000);
-#endif /* defined(CFG_4xx_RESET_TYPE) */
+#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
 #endif /* defined(CONFIG_BOARD_RESET) */
 
 	return 1;
@@ -676,3 +694,15 @@ void reset_4xx_watchdog(void)
 	mtspr(tsr, 0x40000000);
 }
 #endif	/* CONFIG_WATCHDOG */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_PPC4xx_EMAC)
+	ppc_4xx_eth_initialize(bis);
+#endif
+	return 0;
+}
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index dee9807..b5d81f2 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -32,8 +32,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-#ifndef CFG_PLL_RECONFIG
-#define CFG_PLL_RECONFIG	0
+#ifndef CONFIG_SYS_PLL_RECONFIG
+#define CONFIG_SYS_PLL_RECONFIG	0
 #endif
 
 void reconfigure_pll(u32 new_cpu_freq)
@@ -142,32 +142,32 @@ cpu_init_f (void)
 	u32 val;
 #endif
 
-	reconfigure_pll(CFG_PLL_RECONFIG);
+	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
+#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
-#if defined(CFG_GPIO0_OR)
-	out32(GPIO0_OR, CFG_GPIO0_OR);		/* set initial state of output pins	*/
+#if defined(CONFIG_SYS_GPIO0_OR)
+	out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR);		/* set initial state of output pins	*/
 #endif
-#if defined(CFG_GPIO0_ODR)
-	out32(GPIO0_ODR, CFG_GPIO0_ODR);	/* open-drain select			*/
+#if defined(CONFIG_SYS_GPIO0_ODR)
+	out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);	/* open-drain select			*/
 #endif
-	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select			*/
-	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select				*/
-	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select			*/
-	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-#if defined(CFG_GPIO0_ISR2H)
-	out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
-	out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
+	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select			*/
+	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
+	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select				*/
+	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
+	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select			*/
+	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
+#if defined(CONFIG_SYS_GPIO0_ISR2H)
+	out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
+	out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
 #endif
-#if defined (CFG_GPIO0_TCR)
-	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/
+#if defined (CONFIG_SYS_GPIO0_TCR)
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);	/* enable output driver for outputs	*/
 #endif
-#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
 
 #if defined (CONFIG_405EP)
 	/*
@@ -181,14 +181,14 @@ cpu_init_f (void)
 	mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
 #endif /* CONFIG_405EP */
 
-#if defined(CFG_4xx_GPIO_TABLE)
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
 	gpio_set_chip_configuration();
-#endif /* CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
 
 	/*
 	 * External Bus Controller (EBC) Setup
 	 */
-#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
      defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
      defined(CONFIG_405EX) || defined(CONFIG_405))
@@ -209,47 +209,47 @@ cpu_init_f (void)
 	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
 #endif
 
-	mtebc(pb0ap, CFG_EBC_PB0AP);
-	mtebc(pb0cr, CFG_EBC_PB0CR);
+	mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
+	mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
 #endif
 
-#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
-	mtebc(pb1ap, CFG_EBC_PB1AP);
-	mtebc(pb1cr, CFG_EBC_PB1CR);
+#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
+	mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP);
+	mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR);
 #endif
 
-#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
-	mtebc(pb2ap, CFG_EBC_PB2AP);
-	mtebc(pb2cr, CFG_EBC_PB2CR);
+#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
+	mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP);
+	mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR);
 #endif
 
-#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
-	mtebc(pb3ap, CFG_EBC_PB3AP);
-	mtebc(pb3cr, CFG_EBC_PB3CR);
+#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
+	mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP);
+	mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
 #endif
 
-#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
-	mtebc(pb4ap, CFG_EBC_PB4AP);
-	mtebc(pb4cr, CFG_EBC_PB4CR);
+#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
+	mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP);
+	mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR);
 #endif
 
-#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
-	mtebc(pb5ap, CFG_EBC_PB5AP);
-	mtebc(pb5cr, CFG_EBC_PB5CR);
+#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
+	mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP);
+	mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR);
 #endif
 
-#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
-	mtebc(pb6ap, CFG_EBC_PB6AP);
-	mtebc(pb6cr, CFG_EBC_PB6CR);
+#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
+	mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP);
+	mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR);
 #endif
 
-#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
-	mtebc(pb7ap, CFG_EBC_PB7AP);
-	mtebc(pb7cr, CFG_EBC_PB7CR);
+#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
+	mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP);
+	mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR);
 #endif
 
-#if defined (CFG_EBC_CFG)
-	mtebc(EBC0_CFG, CFG_EBC_CFG);
+#if defined (CONFIG_SYS_EBC_CFG)
+	mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
 #endif
 
 #if defined(CONFIG_WATCHDOG)
@@ -261,9 +261,9 @@ cpu_init_f (void)
 #else
 	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
 #endif
-#if defined(CFG_4xx_RESET_TYPE)
+#if defined(CONFIG_SYS_4xx_RESET_TYPE)
 	val &= ~0x30000000;			/* clear WRC bits */
-	val |= CFG_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
+	val |= CONFIG_SYS_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
 #endif
 	mtspr(tcr, val);
 
diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c
index 967e61b..ffc3817 100644
--- a/cpu/ppc4xx/denali_data_eye.c
+++ b/cpu/ppc4xx/denali_data_eye.c
@@ -127,7 +127,7 @@ void denali_core_search_data_eye(void)
 		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55
 	};
 
-	ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
+	ram_pointer = (volatile u32 *)(CONFIG_SYS_SDRAM_BASE);
 
 	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
 		/* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 670fc5c..4705e21 100644
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -1048,8 +1048,8 @@ phys_size_t initdram(int board_type)
 	 * before continuing.
 	 */
 	/* switch to correct I2C bus */
-	I2C_SET_BUS(CFG_SPD_BUS_NUM);
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/*------------------------------------------------------------------
 	 * Clear out the serial presence detect buffers.
@@ -1185,27 +1185,27 @@ phys_size_t initdram(int board_type)
 	 * Map the first 1 MiB of memory in the TLB, and perform the data eye
 	 * search.
 	 */
-	program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
 	denali_core_search_data_eye();
 	denali_sdram_register_dump();
-	remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE);
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
 #endif
 
 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
-	program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
 	sync();
 	/* Zero the memory */
 	debug("Zeroing SDRAM...");
-#if defined(CFG_MEM_TOP_HIDE)
-	dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE);
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+	dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
 #else
-#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
+#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
 #endif
 	/* Write modified dcache lines back to memory */
-	clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
+	clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
 	debug("Completed\n");
 	sync();
-	remove_tlb(CFG_SDRAM_BASE, dram_size);
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
 
 #if defined(CONFIG_DDR_ECC)
 	/*
@@ -1236,7 +1236,7 @@ phys_size_t initdram(int board_type)
 #endif /* defined(CONFIG_DDR_ECC) */
 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
 
-	program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
 	return dram_size;
 }
 
diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c
index a2eb07b..3f989e7 100644
--- a/cpu/ppc4xx/ecc.c
+++ b/cpu/ppc4xx/ecc.c
@@ -68,7 +68,7 @@
  *
  *  Output(s):
  *    start - A pointer to the start of memory covered by ECC with
- *	      CFG_ECC_PATTERN written to all locations and ECC data
+ *	      CONFIG_SYS_ECC_PATTERN written to all locations and ECC data
  *	      primed.
  *
  *  Returns:
@@ -76,7 +76,7 @@
  */
 void ecc_init(unsigned long * const start, unsigned long size)
 {
-	const unsigned long pattern = CFG_ECC_PATTERN;
+	const unsigned long pattern = CONFIG_SYS_ECC_PATTERN;
 	unsigned long * const end = (unsigned long * const)((long)start + size);
 	unsigned long * current = start;
 	unsigned long mcopt1;
diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h
index aecf291..67c3bff 100644
--- a/cpu/ppc4xx/ecc.h
+++ b/cpu/ppc4xx/ecc.h
@@ -33,9 +33,9 @@
 #ifndef _ECC_H_
 #define _ECC_H_
 
-#if !defined(CFG_ECC_PATTERN)
-#define	CFG_ECC_PATTERN	0x00000000
-#endif /* !defined(CFG_ECC_PATTERN) */
+#if !defined(CONFIG_SYS_ECC_PATTERN)
+#define	CONFIG_SYS_ECC_PATTERN	0x00000000
+#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */
 
 /*
  * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index a97484f..c55e1cf 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -37,29 +37,40 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void __ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 val[4];
 	int rc;
+	int i;
+	u32 bxcr;
+	u32 ranges[EBC_NUM_BANKS * 4];
+	u32 *p = ranges;
+	char *ebc_path = "/plb/opb/ebc";
 
 	ft_cpu_setup(blob, bd);
 
-	/* Fixup NOR mapping */
-	val[0] = 0;				/* chip select number */
-	val[1] = 0;				/* always 0 */
-	val[2] = gd->bd->bi_flashstart;
-	val[3] = gd->bd->bi_flashsize;
-	if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) {
-		rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
-					  val, sizeof(val), 1);
-	} else {
-		/*
-		 * Some 405 PPC's have EBC as direct PLB child in the dts
-		 */
-		rc = fdt_find_and_setprop(blob, "/plb/ebc", "ranges",
-					  val, sizeof(val), 1);
+	/*
+	 * Read 4xx EBC bus bridge registers to get mappings of the
+	 * peripheral banks into the OPB/PLB address space
+	 */
+	for (i = 0; i < EBC_NUM_BANKS; i++) {
+		mtdcr(ebccfga, EBC_BXCR(i));
+		bxcr = mfdcr(ebccfgd);
+
+		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
+			*p++ = i;
+			*p++ = 0;
+			*p++ = bxcr & EBC_BXCR_BAS_MASK;
+			*p++ = EBC_BXCR_BANK_SIZE(bxcr);
+		}
 	}
-	if (rc)
-		printf("Unable to update property NOR mapping, err=%s\n",
+
+	/* Some 405 PPC's have EBC as direct PLB child in the dts */
+	if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+		strcpy(ebc_path, "/plb/ebc");
+	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
+				  (p - ranges) * sizeof(u32), 1);
+	if (rc) {
+		printf("Unable to update property EBC mappings, err=%s\n",
 		       fdt_strerror(rc));
+	}
 }
 void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
 
diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
index df99f53..c0d351a 100644
--- a/cpu/ppc4xx/gpio.c
+++ b/cpu/ppc4xx/gpio.c
@@ -26,8 +26,8 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
-#if defined(CFG_4xx_GPIO_TABLE)
-gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
+gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
 #endif
 
 #if defined(GPIO0_OSRL)
@@ -132,7 +132,7 @@ int gpio_read_in_bit(int pin)
 	return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
 }
 
-#if defined(CFG_4xx_GPIO_TABLE)
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
 void gpio_set_chip_configuration(void)
 {
 	unsigned char i=0, j=0, offs=0, gpio_core;
@@ -252,4 +252,4 @@ void gpio_set_chip_configuration(void)
 		}
 	}
 }
-#endif /* CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index d8be2ce..9d416ca 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -42,11 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
  * runs from ROM, and we can't switch buses because we can't modify
  * the global variables.
  */
-#ifdef CFG_SPD_BUS_NUM
-static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
-#else
-static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+#ifndef CONFIG_SYS_SPD_BUS_NUM
+#define CONFIG_SYS_SPD_BUS_NUM	0
 #endif
+static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
 #endif /* CONFIG_I2C_MULTI_BUS */
 
 static void _i2c_bus_reset(void)
@@ -95,14 +94,14 @@ void i2c_init(int speed, int slaveadd)
 	int val, divisor;
 	int bus;
 
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
 	/* call board specific i2c bus reset routine before accessing the   */
 	/* environment, which might be in a chip on that bus. For details   */
 	/* about this problem see doc/I2C_Edge_Conditions.                  */
 	i2c_init_board();
 #endif
 
-	for (bus = 0; bus < CFG_MAX_I2C_BUS; bus++) {
+	for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
 		I2C_SET_BUS(bus);
 
 		/* Handle possible failed I2C state */
@@ -161,7 +160,7 @@ void i2c_init(int speed, int slaveadd)
 	}
 
 	/* set to SPD bus as default bus upon powerup */
-	I2C_SET_BUS(CFG_SPD_BUS_NUM);
+	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 }
 
 /*
@@ -361,7 +360,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
 	}
 
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 	/*
 	 * EEPROM chips that implement "address overflow" are ones
 	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -374,7 +373,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
 	 * hidden in the chip address.
 	 */
 	if (alen > 0)
-		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 	if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
 		if (gd->have_console)
@@ -401,7 +400,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
 		xaddr[3] = addr & 0xFF;
 	}
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 	/*
 	 * EEPROM chips that implement "address overflow" are ones
 	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -414,32 +413,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
 	 * hidden in the chip address.
 	 */
 	if (alen > 0)
-		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 
 	return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
 }
 
-/*-----------------------------------------------------------------------
- * Read a register
- */
-uchar i2c_reg_read(uchar i2c_addr, uchar reg)
-{
-	uchar buf;
-
-	i2c_read(i2c_addr, reg, 1, &buf, 1);
-
-	return (buf);
-}
-
-/*-----------------------------------------------------------------------
- * Write a register
- */
-void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
-{
-	i2c_write(i2c_addr, reg, 1, &val, 1);
-}
-
 #if defined(CONFIG_I2C_MULTI_BUS)
 /*
  * Functions for multiple I2C bus handling
@@ -451,7 +430,7 @@ unsigned int i2c_get_bus_num(void)
 
 int i2c_set_bus_num(unsigned int bus)
 {
-	if (bus >= CFG_MAX_I2C_BUS)
+	if (bus >= CONFIG_SYS_MAX_I2C_BUS)
 		return -1;
 
 	i2c_bus_num = bus;
@@ -463,12 +442,12 @@ int i2c_set_bus_num(unsigned int bus)
 /* TODO: add 100/400k switching */
 unsigned int i2c_get_bus_speed(void)
 {
-	return CFG_I2C_SPEED;
+	return CONFIG_SYS_I2C_SPEED;
 }
 
 int i2c_set_bus_speed(unsigned int speed)
 {
-	if (speed != CFG_I2C_SPEED)
+	if (speed != CONFIG_SYS_I2C_SPEED)
 		return -1;
 
 	return 0;
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index c882720..01710e7 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -180,8 +180,10 @@ int phy_setup_aneg (char *devname, unsigned char addr)
  *
  * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
  * return EMAC0 offset here
+ * vg: For 460EX/460GT if internal GPCS PHY address is specified
+ * return appropriate EMAC offset
  */
-unsigned int miiphy_getemac_offset (void)
+unsigned int miiphy_getemac_offset(u8 addr)
 {
 #if (defined(CONFIG_440) && \
     !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@@ -233,6 +235,35 @@ unsigned int miiphy_getemac_offset (void)
 		return 0x100;
 #endif
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	u32 eoffset = 0;
+
+	switch (addr) {
+#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
+	case CONFIG_GPCS_PHY1_ADDR:
+		if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100)))
+			eoffset = 0x100;
+		break;
+#endif
+#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
+	case CONFIG_GPCS_PHY2_ADDR:
+		if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300)))
+			eoffset = 0x300;
+		break;
+#endif
+#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
+	case CONFIG_GPCS_PHY3_ADDR:
+		if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400)))
+			eoffset = 0x400;
+		break;
+#endif
+	default:
+		eoffset = 0;
+		break;
+	}
+	return eoffset;
+#endif
+
 	return 0;
 #endif
 }
@@ -262,7 +293,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
 	u32 emac_reg;
 	u32 sta_reg;
 
-	emac_reg = miiphy_getemac_offset();
+	emac_reg = miiphy_getemac_offset(addr);
 
 	/* wait for completion */
 	if (emac_miiphy_wait(emac_reg) != 0)
@@ -270,7 +301,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
 
 	sta_reg = reg;		/* reg address */
 
-	/* set clock (50Mhz) and read flags */
+	/* set clock (50MHz) and read flags */
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
@@ -311,7 +342,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg,
 	unsigned long sta_reg;
 	unsigned long emac_reg;
 
-	emac_reg = miiphy_getemac_offset ();
+	emac_reg = miiphy_getemac_offset(addr);
 
 	if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
 		return -1;
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 7d96e79..3a5af12 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -149,8 +149,8 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 }
 #endif /* #ifndef CONFIG_NAND_SPL */
 
-#ifndef CFG_NAND_BCR
-#define CFG_NAND_BCR 0x80002222
+#ifndef CONFIG_SYS_NAND_BCR
+#define CONFIG_SYS_NAND_BCR 0x80002222
 #endif
 
 void board_nand_select_device(struct nand_chip *nand, int chip)
@@ -165,7 +165,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
 	/* Set NandFlash Core Configuration Register */
 	/* 1 col x 2 rows */
 	out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
-	out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CFG_NAND_BCR);
+	out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
 }
 
 static void ndfc_select_chip(struct mtd_info *mtd, int chip)
@@ -214,8 +214,8 @@ int board_nand_init(struct nand_chip *nand)
 	 */
 	mtebc(EBC0_CFG, 0xb8400000);
 
-	mtebc(pb0cr, CFG_EBC_PB0CR);
-	mtebc(pb0ap, CFG_EBC_PB0AP);
+	mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
+	mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
 #endif
 
 	chip++;
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 7d60ad6..6d5f8d6 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -37,7 +37,7 @@
 
 #ifndef CONFIG_440
 
-#ifndef CFG_SDRAM_TABLE
+#ifndef CONFIG_SYS_SDRAM_TABLE
 sdram_conf_t mb0cf[] = {
 	{(128 << 20), 13, 0x000A4001},	    /* (0-128MB) Address Mode 3, 13x10(4) */
 	{(64 << 20),  13, 0x00084001},	    /* (0-64MB) Address Mode 3, 13x9(4)	  */
@@ -46,72 +46,72 @@ sdram_conf_t mb0cf[] = {
 	{(4 << 20),   11, 0x00008001},	    /* (0-4MB) Address Mode 5, 11x8(2)	  */
 };
 #else
-sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 #endif
 
 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
 
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
 static ulong ns2clks(ulong ns)
 {
 	ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
 
 	return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
 }
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
 
 static ulong compute_sdtr1(ulong speed)
 {
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
 	ulong tmp;
 	ulong sdtr1 = 0;
 
 	/* CASL */
-	if (CFG_SDRAM_CASL < 2)
+	if (CONFIG_SYS_SDRAM_CASL < 2)
 		sdtr1 |= (1 << SDRAM0_TR_CASL);
 	else
-		if (CFG_SDRAM_CASL > 4)
+		if (CONFIG_SYS_SDRAM_CASL > 4)
 			sdtr1 |= (3 << SDRAM0_TR_CASL);
 		else
-			sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL);
+			sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
 
 	/* PTA */
-	tmp = ns2clks(CFG_SDRAM_PTA);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
 	if ((tmp >= 2) && (tmp <= 4))
 		sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
 	else
 		sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
 
 	/* CTP */
-	tmp = ns2clks(CFG_SDRAM_CTP);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
 	if ((tmp >= 2) && (tmp <= 4))
 		sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
 	else
 		sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
 
 	/* LDF */
-	tmp = ns2clks(CFG_SDRAM_LDF);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
 	if ((tmp >= 2) && (tmp <= 4))
 		sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
 	else
 		sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
 
 	/* RFTA */
-	tmp = ns2clks(CFG_SDRAM_RFTA);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
 	if ((tmp >= 4) && (tmp <= 10))
 		sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
 	else
 		sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
 
 	/* RCD */
-	tmp = ns2clks(CFG_SDRAM_RCD);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
 	if ((tmp >= 2) && (tmp <= 4))
 		sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
 	else
 		sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
 
 	return sdtr1;
-#else /* CFG_SDRAM_CASL */
+#else /* CONFIG_SYS_SDRAM_CASL */
 	/*
 	 * If no values are configured in the board config file
 	 * use the default values, which seem to be ok for most
@@ -133,20 +133,20 @@ static ulong compute_sdtr1(ulong speed)
 		 */
 		return 0x0086400d;
 	}
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
 }
 
 /* refresh is expressed in ms */
 static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 {
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
 	ulong tmp;
 
 	tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
 	tmp /= 1000000;
 
 	return ((tmp & 0x00003FF8) << 16);
-#else /* CFG_SDRAM_CASL */
+#else /* CONFIG_SYS_SDRAM_CASL */
 	if (speed > 100000000) {
 		/*
 		 * 133 MHz SDRAM
@@ -158,7 +158,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 		 */
 		return 0x05f00000;
 	}
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
 }
 
 /*
@@ -209,15 +209,15 @@ phys_size_t initdram(int board_type)
 		udelay(10000);
 
 		if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+			phys_size_t size = mb0cf[i].size;
+
 			/*
 			 * OK, size detected.  Enable second bank if
 			 * defined (assumes same type as bank 0)
 			 */
 #ifdef CONFIG_SDRAM_BANK1
-			u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
-
 			mtsdram(mem_mcopt1, 0x00000000);
-			mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+			mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
 			mtsdram(mem_mcopt1, 0x80800000);
 			udelay(10000);
 
@@ -230,13 +230,19 @@ phys_size_t initdram(int board_type)
 			    mb0cf[i].size) {
 				mtsdram(mem_mb1cf, 0);
 				mtsdram(mem_mcopt1, 0);
+			} else {
+				/*
+				 * We have two identical banks, so the size
+				 * is twice the bank size
+				 */
+				size = 2 * size;
 			}
 #endif
 
 			/*
 			 * OK, size detected -> all done
 			 */
-			return mb0cf[i].size;
+			return size;
 		}
 	}
 
@@ -250,17 +256,17 @@ phys_size_t initdram(int board_type)
  * board config file.
  */
 
-#ifndef CFG_SDRAM_TABLE
+#ifndef CONFIG_SYS_SDRAM_TABLE
 sdram_conf_t mb0cf[] = {
 	{(256 << 20), 13, 0x000C4001},	/* 256MB mode 3, 13x10(4)	*/
 	{(64 << 20),  12, 0x00082001}	/* 64MB mode 2, 12x9(4)		*/
 };
 #else
-sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 #endif
 
-#ifndef CFG_SDRAM0_TR0
-#define	CFG_SDRAM0_TR0		0x41094012
+#ifndef CONFIG_SYS_SDRAM0_TR0
+#define	CONFIG_SYS_SDRAM0_TR0		0x41094012
 #endif
 
 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
@@ -379,7 +385,7 @@ phys_size_t initdram(int board_type)
 		 * Following for CAS Latency = 2.5 @ 133 MHz PLB
 		 */
 		mtsdram(mem_b0cr, mb0cf[i].reg);
-		mtsdram(mem_tr0, CFG_SDRAM0_TR0);
+		mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
 		mtsdram(mem_tr1, 0x80800800);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
 		mtsdram(mem_rtr, 0x04100000);	/* Interval 7.8µs @ 133MHz PLB	*/
 		mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM*/
diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h
index 4fb9b1a..bea3376 100644
--- a/cpu/ppc4xx/sdram.h
+++ b/cpu/ppc4xx/sdram.h
@@ -47,19 +47,19 @@ typedef struct sdram_conf_s sdram_conf_t;
 #define SDRAM0_TR_RFTA		(31 - 29)
 #define SDRAM0_TR_RCD		(31 - 31)
 
-#ifdef CFG_SDRAM_CL
+#ifdef CONFIG_SYS_SDRAM_CL
 /* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */
-#define CFG_SDRAM_CASL		CFG_SDRAM_CL
-#define CFG_SDRAM_PTA		CFG_SDRAM_tRP
-#define CFG_SDRAM_CTP		(CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP)
-#define CFG_SDRAM_LDF		0
-#ifdef CFG_SDRAM_tRFC
-#define CFG_SDRAM_RFTA		CFG_SDRAM_tRFC
+#define CONFIG_SYS_SDRAM_CASL		CONFIG_SYS_SDRAM_CL
+#define CONFIG_SYS_SDRAM_PTA		CONFIG_SYS_SDRAM_tRP
+#define CONFIG_SYS_SDRAM_CTP		(CONFIG_SYS_SDRAM_tRC - CONFIG_SYS_SDRAM_tRCD - CONFIG_SYS_SDRAM_tRP)
+#define CONFIG_SYS_SDRAM_LDF		0
+#ifdef CONFIG_SYS_SDRAM_tRFC
+#define CONFIG_SYS_SDRAM_RFTA		CONFIG_SYS_SDRAM_tRFC
 #else
-#define CFG_SDRAM_RFTA		CFG_SDRAM_tRC
+#define CONFIG_SYS_SDRAM_RFTA		CONFIG_SYS_SDRAM_tRC
 #endif
-#define CFG_SDRAM_RCD		CFG_SDRAM_tRCD
-#endif /* #ifdef CFG_SDRAM_CL */
+#define CONFIG_SYS_SDRAM_RCD		CONFIG_SYS_SDRAM_tRCD
+#endif /* #ifdef CONFIG_SYS_SDRAM_CL */
 
 /*
  * Some defines for the 440 DDR controller
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index d21bd82..ed6e55b 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -148,7 +148,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
 		 * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
 		 * to make sure it is within the proper range.
 		 *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
-		 * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
+		 * Note freqVCO is calculated in MHz to avoid errors introduced by rounding.
 		 */
 		if (sysInfo->pllFwdDiv == 1) {
 			sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 97411bd..f2b8908 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -63,6 +63,7 @@
  */
 #include <config.h>
 #include <ppc4xx.h>
+#include <timestamp.h>
 #include <version.h>
 
 #define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
@@ -72,74 +73,75 @@
 
 #include <asm/cache.h>
 #include <asm/mmu.h>
+#include <asm/ppc4xx-isram.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-#ifdef CFG_INIT_DCACHE_CS
-# if (CFG_INIT_DCACHE_CS == 0)
+#ifdef CONFIG_SYS_INIT_DCACHE_CS
+# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
 #  define PBxAP pb0ap
 #  define PBxCR pb0cr
-#  if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
-#   define PBxAP_VAL CFG_EBC_PB0AP
-#   define PBxCR_VAL CFG_EBC_PB0CR
+#  if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 1)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 1)
 #  define PBxAP pb1ap
 #  define PBxCR pb1cr
-#  if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
-#   define PBxAP_VAL CFG_EBC_PB1AP
-#   define PBxCR_VAL CFG_EBC_PB1CR
+#  if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 2)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 2)
 #  define PBxAP pb2ap
 #  define PBxCR pb2cr
-#  if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
-#   define PBxAP_VAL CFG_EBC_PB2AP
-#   define PBxCR_VAL CFG_EBC_PB2CR
+#  if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 3)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 3)
 #  define PBxAP pb3ap
 #  define PBxCR pb3cr
-#  if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
-#   define PBxAP_VAL CFG_EBC_PB3AP
-#   define PBxCR_VAL CFG_EBC_PB3CR
+#  if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 4)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 4)
 #  define PBxAP pb4ap
 #  define PBxCR pb4cr
-#  if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
-#   define PBxAP_VAL CFG_EBC_PB4AP
-#   define PBxCR_VAL CFG_EBC_PB4CR
+#  if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 5)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 5)
 #  define PBxAP pb5ap
 #  define PBxCR pb5cr
-#  if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
-#   define PBxAP_VAL CFG_EBC_PB5AP
-#   define PBxCR_VAL CFG_EBC_PB5CR
+#  if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 6)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 6)
 #  define PBxAP pb6ap
 #  define PBxCR pb6cr
-#  if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
-#   define PBxAP_VAL CFG_EBC_PB6AP
-#   define PBxCR_VAL CFG_EBC_PB6CR
+#  if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 7)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 7)
 #  define PBxAP pb7ap
 #  define PBxCR pb7cr
-#  if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
-#   define PBxAP_VAL CFG_EBC_PB7AP
-#   define PBxCR_VAL CFG_EBC_PB7CR
+#  if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
 #  endif
 # endif
 # ifndef PBxAP_VAL
@@ -149,11 +151,11 @@
 #  define PBxCR_VAL	0
 # endif
 /*
- * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB
+ * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
  * used as temporary stack pointer for the primordial stack
  */
-# ifndef CFG_INIT_DCACHE_PBxAR
-#  define CFG_INIT_DCACHE_PBxAR	(EBC_BXAP_BME_DISABLED			| \
+# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
+#  define CONFIG_SYS_INIT_DCACHE_PBxAR	(EBC_BXAP_BME_DISABLED			| \
 				 EBC_BXAP_TWT_ENCODE(7)			| \
 				 EBC_BXAP_BCE_DISABLE			| \
 				 EBC_BXAP_BCT_2TRANS			| \
@@ -166,42 +168,42 @@
 				 EBC_BXAP_SOR_NONDELAYED		| \
 				 EBC_BXAP_BEM_WRITEONLY			| \
 				 EBC_BXAP_PEN_DISABLED)
-# endif /* CFG_INIT_DCACHE_PBxAR */
-# ifndef CFG_INIT_DCACHE_PBxCR
-#  define CFG_INIT_DCACHE_PBxCR	(EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR)	| \
+# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
+# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
+#  define CONFIG_SYS_INIT_DCACHE_PBxCR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR)	| \
 				 EBC_BXCR_BS_64MB			| \
 				 EBC_BXCR_BU_RW				| \
 				 EBC_BXCR_BW_16BIT)
-# endif /* CFG_INIT_DCACHE_PBxCR */
-# ifndef CFG_INIT_RAM_PATTERN
-#  define CFG_INIT_RAM_PATTERN	0xDEADDEAD
+# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
+# ifndef CONFIG_SYS_INIT_RAM_PATTERN
+#  define CONFIG_SYS_INIT_RAM_PATTERN	0xDEADDEAD
 # endif
-#endif /* CFG_INIT_DCACHE_CS */
+#endif /* CONFIG_SYS_INIT_DCACHE_CS */
 
-#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
-#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
+#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
+#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
 #endif
 
 /*
  * Unless otherwise overriden, enable two 128MB cachable instruction regions
- * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering
- * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions.
+ * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
+ * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
  */
-#if !defined(CFG_FLASH_BASE)
+#if !defined(CONFIG_SYS_FLASH_BASE)
 /* If not already defined, set it to the "last" 128MByte region */
-# define CFG_FLASH_BASE		0xf8000000
+# define CONFIG_SYS_FLASH_BASE		0xf8000000
 #endif
-#if !defined(CFG_ICACHE_SACR_VALUE)
-# define CFG_ICACHE_SACR_VALUE		\
-		(PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (  0 << 20)) | \
-		 PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \
-		 PPC_128MB_SACR_VALUE(CFG_FLASH_BASE))
-#endif /* !defined(CFG_ICACHE_SACR_VALUE) */
-
-#if !defined(CFG_DCACHE_SACR_VALUE)
-# define CFG_DCACHE_SACR_VALUE		\
+#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
+# define CONFIG_SYS_ICACHE_SACR_VALUE		\
+		(PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (  0 << 20)) | \
+		 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
+		 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
+#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
+
+#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
+# define CONFIG_SYS_DCACHE_SACR_VALUE		\
 		(0x00000000)
-#endif /* !defined(CFG_DCACHE_SACR_VALUE) */
+#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
 
 #define function_prolog(func_name)	.text; \
 					.align 2; \
@@ -509,7 +511,7 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
 	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
-	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
 	.ascii CONFIG_IDENT_STRING, "\0"
 
 	. = EXC_OFF_SYS_RESET
@@ -609,15 +611,15 @@ _start:
 
 	/*----------------------------------------------------------------*/
 	/* Debug setup -- some (not very good) ice's need an event*/
-	/* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
+	/* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
 	/* value you need in this case 0x8cff 0000 should do the trick */
 	/*----------------------------------------------------------------*/
-#if defined(CFG_INIT_DBCR)
+#if defined(CONFIG_SYS_INIT_DBCR)
 	lis	r1,0xffff
 	ori	r1,r1,0xffff
 	mtspr	dbsr,r1			/* Clear all status bits */
-	lis	r0,CFG_INIT_DBCR@h
-	ori	r0,r0,CFG_INIT_DBCR@l
+	lis	r0,CONFIG_SYS_INIT_DBCR@h
+	ori	r0,r0,CONFIG_SYS_INIT_DBCR@l
 	mtspr	dbcr0,r0
 	isync
 #endif
@@ -627,12 +629,12 @@ _start:
 	/*----------------------------------------------------------------*/
 	li	r0,0
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* Clear Dcache to use as RAM */
-	addis	r3,r0,CFG_INIT_RAM_ADDR@h
-	ori	r3,r3,CFG_INIT_RAM_ADDR@l
-	addis	r4,r0,CFG_INIT_RAM_END@h
-	ori	r4,r4,CFG_INIT_RAM_END@l
+	addis	r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+	addis	r4,r0,CONFIG_SYS_INIT_RAM_END@h
+	ori	r4,r4,CONFIG_SYS_INIT_RAM_END@l
 	rlwinm. r5,r4,0,27,31
 	rlwinm	r5,r4,27,5,31
 	beq	..d_ran
@@ -670,82 +672,95 @@ _start:
 	mtspr	dtv3,r1
 	msync
 	isync
-#endif /* CFG_INIT_RAM_DCACHE */
+#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 
 	/* 440EP & 440GR are only 440er PPC's without internal SRAM */
 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
 	/* not all PPC's have internal SRAM usable as L2-cache */
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_460SX)
-	mtdcr	l2_cache_cfg,r0		/* Ensure L2 Cache is off */
+	mtdcr	L2_CACHE_CFG,r0		/* Ensure L2 Cache is off */
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	lis	r1, 0x0000
+	ori	r1,r1,0x0008		/* Set L2_CACHE_CFG[RDBW]=1 */
+	mtdcr	L2_CACHE_CFG,r1
 #endif
 
 	lis	r2,0x7fff
 	ori	r2,r2,0xffff
-	mfdcr	r1,isram0_dpc
+	mfdcr	r1,ISRAM0_DPC
 	and	r1,r1,r2		/* Disable parity check */
-	mtdcr	isram0_dpc,r1
-	mfdcr	r1,isram0_pmeg
+	mtdcr	ISRAM0_DPC,r1
+	mfdcr	r1,ISRAM0_PMEG
 	and	r1,r1,r2		/* Disable pwr mgmt */
-	mtdcr	isram0_pmeg,r1
+	mtdcr	ISRAM0_PMEG,r1
 
 	lis	r1,0x8000		/* BAS = 8000_0000 */
 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 	ori	r1,r1,0x0980		/* first 64k */
-	mtdcr	isram0_sb0cr,r1
+	mtdcr	ISRAM0_SB0CR,r1
 	lis	r1,0x8001
 	ori	r1,r1,0x0980		/* second 64k */
-	mtdcr	isram0_sb1cr,r1
+	mtdcr	ISRAM0_SB1CR,r1
 	lis	r1, 0x8002
 	ori	r1,r1, 0x0980		/* third 64k */
-	mtdcr	isram0_sb2cr,r1
+	mtdcr	ISRAM0_SB2CR,r1
 	lis	r1, 0x8003
 	ori	r1,r1, 0x0980		/* fourth 64k */
-	mtdcr	isram0_sb3cr,r1
-#elif defined(CONFIG_440SPE)
-	lis	r1,0x0000		/* BAS = 0000_0000 */
+	mtdcr	ISRAM0_SB3CR,r1
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	lis	r1,0x0000		/* BAS = X_0000_0000 */
 	ori	r1,r1,0x0984		/* first 64k */
-	mtdcr	isram0_sb0cr,r1
+	mtdcr	ISRAM0_SB0CR,r1
 	lis	r1,0x0001
 	ori	r1,r1,0x0984		/* second 64k */
-	mtdcr	isram0_sb1cr,r1
+	mtdcr	ISRAM0_SB1CR,r1
 	lis	r1, 0x0002
 	ori	r1,r1, 0x0984		/* third 64k */
-	mtdcr	isram0_sb2cr,r1
+	mtdcr	ISRAM0_SB2CR,r1
 	lis	r1, 0x0003
 	ori	r1,r1, 0x0984		/* fourth 64k */
-	mtdcr	isram0_sb3cr,r1
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	lis	r1,0x4000		/* BAS = 8000_0000 */
-	ori	r1,r1,0x4580		/* 16k */
-	mtdcr	isram0_sb0cr,r1
+	mtdcr	ISRAM0_SB3CR,r1
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	lis	r2,0x7fff
+	ori	r2,r2,0xffff
+	mfdcr	r1,ISRAM1_DPC
+	and	r1,r1,r2		/* Disable parity check */
+	mtdcr	ISRAM1_DPC,r1
+	mfdcr	r1,ISRAM1_PMEG
+	and	r1,r1,r2		/* Disable pwr mgmt */
+	mtdcr	ISRAM1_PMEG,r1
+
+	lis	r1,0x0004		/* BAS = 4_0004_0000 */
+	ori	r1,r1,0x0984		/* 64k */
+	mtdcr	ISRAM1_SB0CR,r1
+#endif
 #elif defined(CONFIG_460SX)
 	lis     r1,0x0000               /* BAS = 0000_0000 */
 	ori     r1,r1,0x0B84            /* first 128k */
-	mtdcr   isram0_sb0cr,r1
+	mtdcr   ISRAM0_SB0CR,r1
 	lis     r1,0x0001
 	ori     r1,r1,0x0B84            /* second 128k */
-	mtdcr   isram0_sb1cr,r1
+	mtdcr   ISRAM0_SB1CR,r1
 	lis     r1, 0x0002
 	ori     r1,r1, 0x0B84           /* third 128k */
-	mtdcr   isram0_sb2cr,r1
+	mtdcr   ISRAM0_SB2CR,r1
 	lis     r1, 0x0003
 	ori     r1,r1, 0x0B84           /* fourth 128k */
-	mtdcr   isram0_sb3cr,r1
+	mtdcr   ISRAM0_SB3CR,r1
 #elif defined(CONFIG_440GP)
 	ori	r1,r1,0x0380		/* 8k rw */
-	mtdcr	isram0_sb0cr,r1
-	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
+	mtdcr	ISRAM0_SB0CR,r1
+	mtdcr	ISRAM0_SB1CR,r0		/* Disable bank 1 */
 #endif
 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 
 	/*----------------------------------------------------------------*/
 	/* Setup the stack in internal SRAM */
 	/*----------------------------------------------------------------*/
-	lis	r1,CFG_INIT_RAM_ADDR@h
-	ori	r1,r1,CFG_INIT_SP_OFFSET@l
+	lis	r1,CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
 	li	r0,0
 	stwu	r0,-4(r1)
 	stwu	r0,-4(r1)		/* Terminate call chain */
@@ -852,18 +867,18 @@ _start:
 	sync
 
 	/* Set-up icache cacheability. */
-	lis	r1, CFG_ICACHE_SACR_VALUE@h
-	ori	r1, r1, CFG_ICACHE_SACR_VALUE@l
+	lis	r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
+	ori	r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
 	mticcr	r1
 	isync
 
 	/* Set-up dcache cacheability. */
-	lis	r1, CFG_DCACHE_SACR_VALUE@h
-	ori	r1, r1, CFG_DCACHE_SACR_VALUE@l
+	lis	r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
+	ori	r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
 	mtdccr	r1
 
-	addis	r1,r0,CFG_INIT_RAM_ADDR@h
-	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
+	addis	r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
 	li	r0, 0			/* Make room for stack frame header and */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
@@ -908,31 +923,32 @@ _start:
 	bl	invalidate_dcache
 
 	/* Set-up icache cacheability. */
-	lis	r4, CFG_ICACHE_SACR_VALUE@h
-	ori	r4, r4, CFG_ICACHE_SACR_VALUE@l
+	lis	r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
+	ori	r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
 	mticcr	r4
 	isync
 
 	/* Set-up dcache cacheability. */
-	lis	r4, CFG_DCACHE_SACR_VALUE@h
-	ori	r4, r4, CFG_DCACHE_SACR_VALUE@l
+	lis	r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
+	ori	r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
 	mtdccr	r4
 
-#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
+				&& !defined (CONFIG_XILINX_405)
 	/*----------------------------------------------------------------------- */
 	/* Tune the speed and size for flash CS0  */
 	/*----------------------------------------------------------------------- */
 	bl	ext_bus_cntlr_init
 #endif
 
-#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
+#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
 	/*
 	 * For boards that don't have OCM and can't use the data cache
 	 * for their primordial stack, setup stack here directly after the
 	 * SDRAM is initialized in ext_bus_cntlr_init.
 	 */
-	lis	r1, CFG_INIT_RAM_ADDR@h
-	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
+	lis	r1, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
 
 	li	r0, 0			/* Make room for stack frame header and */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
@@ -946,7 +962,7 @@ _start:
 	ori	r0, r0, RESET_VECTOR@l
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
-#endif /* !(CFG_INIT_DCACHE_CS	|| !CFG_TEM_STACK_OCM) */
+#endif /* !(CONFIG_SYS_INIT_DCACHE_CS	|| !CONFIG_SYS_TEM_STACK_OCM) */
 
 #if defined(CONFIG_405EP)
 	/*----------------------------------------------------------------------- */
@@ -959,25 +975,25 @@ _start:
 	bl	ppc405ep_init		/* do ppc405ep specific init */
 #endif /* CONFIG_405EP */
 
-#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
+#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
 #if defined(CONFIG_405EZ)
 	/********************************************************************
 	 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
 	 *******************************************************************/
 	/*
 	 * We can map the OCM on the PLB3, so map it at
-	 * CFG_OCM_DATA_ADDR + 0x8000
+	 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
 	 */
-	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
-	ori	r3,r3,CFG_OCM_DATA_ADDR@l
+	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
+	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
 	mtdcr	ocmplb3cr1,r3		/* Set PLB Access */
 	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
 	mtdcr	ocmplb3cr2,r3		/* Set PLB Access */
 	isync
 
-	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
-	ori	r3,r3,CFG_OCM_DATA_ADDR@l
+	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
+	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
 	mtdcr	ocmdscr1, r3		/* Set Data Side */
 	mtdcr	ocmiscr1, r3		/* Set Instruction Side */
@@ -1003,8 +1019,8 @@ _start:
 	mtdcr	ocmdscntl, r4		/* set data-side IRAM config */
 	isync
 
-	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
-	ori	r3,r3,CFG_OCM_DATA_ADDR@l
+	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
+	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 	mtdcr	ocmdsarc, r3
 	addis	r4, 0, 0xC000		/* OCM data area enabled */
 	mtdcr	ocmdscntl, r4
@@ -1015,26 +1031,26 @@ _start:
 	/*----------------------------------------------------------------------- */
 	/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 	/*----------------------------------------------------------------------- */
-#ifdef CFG_INIT_DCACHE_CS
+#ifdef CONFIG_SYS_INIT_DCACHE_CS
 	li	r4, PBxAP
 	mtdcr	ebccfga, r4
-	lis	r4, CFG_INIT_DCACHE_PBxAR@h
-	ori	r4, r4, CFG_INIT_DCACHE_PBxAR@l
+	lis	r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
+	ori	r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
 	mtdcr	ebccfgd, r4
 
 	addi	r4, 0, PBxCR
 	mtdcr	ebccfga, r4
-	lis	r4, CFG_INIT_DCACHE_PBxCR@h
-	ori	r4, r4, CFG_INIT_DCACHE_PBxCR@l
+	lis	r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
+	ori	r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
 	mtdcr	ebccfgd, r4
 
 	/*
 	 * Enable the data cache for the 128MB storage access control region
-	 * at CFG_INIT_RAM_ADDR.
+	 * at CONFIG_SYS_INIT_RAM_ADDR.
 	 */
 	mfdccr	r4
-	oris	r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
-	ori	r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
+	oris	r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
 	mtdccr	r4
 
 	/*
@@ -1044,11 +1060,11 @@ _start:
 	 */
 	li	r0, 0
 
-	lis	r3, CFG_INIT_RAM_ADDR@h
-	ori	r3, r3, CFG_INIT_RAM_ADDR@l
+	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 
-	lis	r4, CFG_INIT_RAM_END@h
-	ori	r4, r4, CFG_INIT_RAM_END@l
+	lis	r4, CONFIG_SYS_INIT_RAM_END@h
+	ori	r4, r4, CONFIG_SYS_INIT_RAM_END@l
 
 	/*
 	 * Convert the size, in bytes, to the number of cache lines/blocks
@@ -1072,18 +1088,18 @@ _start:
 	 * Load the initial stack pointer and data area and convert the size,
 	 * in bytes, to the number of words to initialize to a known value.
 	 */
-	lis	r1, CFG_INIT_RAM_ADDR@h
-	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+	lis	r1, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 
-	lis	r4, (CFG_INIT_RAM_END >> 2)@h
-	ori	r4, r4, (CFG_INIT_RAM_END >> 2)@l
+	lis	r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
+	ori	r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
 	mtctr	r4
 
-	lis	r2, CFG_INIT_RAM_ADDR@h
-	ori	r2, r2, CFG_INIT_RAM_END@l
+	lis	r2, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r2, r2, CONFIG_SYS_INIT_RAM_END@l
 
-	lis	r4, CFG_INIT_RAM_PATTERN@h
-	ori	r4, r4, CFG_INIT_RAM_PATTERN@l
+	lis	r4, CONFIG_SYS_INIT_RAM_PATTERN@h
+	ori	r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
 
 ..stackloop:
 	stwu	r4, -4(r2)
@@ -1106,15 +1122,15 @@ _start:
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
 
-#elif defined(CFG_TEMP_STACK_OCM) && \
-	(defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
+#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
+	(defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
 	/*
 	 * Stack in OCM.
 	 */
 
 	/* Set up Stack at top of OCM */
-	lis	r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
-	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
+	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
+	ori	r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
 
 	/* Set up a zeroized stack frame so that backtrace works right */
 	li	r0, 0
@@ -1130,7 +1146,7 @@ _start:
 	ori	r0, r0, RESET_VECTOR@l
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
-#endif /* CFG_INIT_DCACHE_CS */
+#endif /* CONFIG_SYS_INIT_DCACHE_CS */
 
 #ifdef CONFIG_NAND_SPL
 	bl	nand_boot_common	/* will not return */
@@ -1341,7 +1357,7 @@ in32r:
  */
 	.globl	relocate_code
 relocate_code:
-#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS)
+#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
 	/*
 	 * We need to flush the initial global data (gd_t) before the dcache
 	 * will be invalidated.
@@ -1354,10 +1370,10 @@ relocate_code:
 
 	/* Flush initial global data range */
 	mr	r3, r4
-	addi	r4, r4, CFG_GBL_DATA_SIZE@l
+	addi	r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
 	bl	flush_dcache_range
 
-#if defined(CFG_INIT_DCACHE_CS)
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
 	/*
 	 * Undo the earlier data cache set-up for the primordial stack and
 	 * data area. First, invalidate the data cache and then disable data
@@ -1366,19 +1382,19 @@ relocate_code:
 	 */
 
 	/* Invalidate the primordial stack and data area in cache */
-	lis	r3, CFG_INIT_RAM_ADDR@h
-	ori	r3, r3, CFG_INIT_RAM_ADDR@l
+	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 
-	lis	r4, CFG_INIT_RAM_END@h
-	ori	r4, r4, CFG_INIT_RAM_END@l
+	lis	r4, CONFIG_SYS_INIT_RAM_END@h
+	ori	r4, r4, CONFIG_SYS_INIT_RAM_END@l
 	add	r4, r4, r3
 
 	bl	invalidate_dcache_range
 
 	/* Disable cacheability for the region */
 	mfdccr	r3
-	lis     r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
-	ori     r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
+	lis     r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori     r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
 	and     r3, r3, r4
 	mtdccr  r3
 
@@ -1394,15 +1410,15 @@ relocate_code:
 	lis	r3, PBxCR_VAL@h
 	ori	r3, r3, PBxCR_VAL@l
 	mtdcr	ebccfgd, r3
-#endif /* defined(CFG_INIT_DCACHE_CS) */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
 	/* Restore registers */
 	mr	r3, r9
 	mr	r4, r10
 	mr	r5, r11
-#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */
+#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/*
 	 * Unlock the previously locked d-cache
 	 */
@@ -1424,7 +1440,7 @@ relocate_code:
 	mtspr	dtv3,r6
 	msync
 	isync
-#endif /* CFG_INIT_RAM_DCACHE */
+#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@@ -1439,11 +1455,15 @@ relocate_code:
 	dccci	0,0			/* Invalidate data cache, now no longer our stack */
 	sync
 	isync
-#ifdef CFG_TLB_FOR_BOOT_FLASH
-	addi	r1,r0,CFG_TLB_FOR_BOOT_FLASH	/* Use defined TLB */
+
+	/* Clear all potential pending exceptions */
+	mfspr	r1,mcsr
+	mtspr	mcsr,r1
+#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
+	addi	r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH	/* Use defined TLB */
 #else
 	addi	r1,r0,0x0000		/* Default TLB entry is #0 */
-#endif /* CFG_TLB_FOR_BOOT_FLASH */
+#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
 	tlbre	r0,r1,0x0002		/* Read contents */
 	ori	r0,r0,0x0c00		/* Or in the inhibit, write through bit */
 	tlbwe	r0,r1,0x0002		/* Save it out */
@@ -1455,8 +1475,8 @@ relocate_code:
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
 	mr	r3,  r5				/* Destination Address	*/
-	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
-	ori	r4, r4, CFG_MONITOR_BASE@l
+	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
+	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
 	lwz	r5, GOT(__init_end)
 	sub	r5, r5, r4
 	li	r6, L1_CACHE_BYTES		/* Cache Line Size	*/
@@ -1464,7 +1484,7 @@ relocate_code:
 	/*
 	 * Fix GOT pointer:
 	 *
-	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 	 *
 	 * Offset:
 	 */
@@ -1775,74 +1795,74 @@ ppc405ep_init:
 
 	lis	r3,GPIO0_OSRH@h		/* config GPIO output select */
 	ori	r3,r3,GPIO0_OSRH@l
-	lis	r4,CFG_GPIO0_OSRH@h
-	ori	r4,r4,CFG_GPIO0_OSRH@l
+	lis	r4,CONFIG_SYS_GPIO0_OSRH@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_OSRH@l
 	stw	r4,0(r3)
 	lis	r3,GPIO0_OSRL@h
 	ori	r3,r3,GPIO0_OSRL@l
-	lis	r4,CFG_GPIO0_OSRL@h
-	ori	r4,r4,CFG_GPIO0_OSRL@l
+	lis	r4,CONFIG_SYS_GPIO0_OSRL@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_OSRL@l
 	stw	r4,0(r3)
 
 	lis	r3,GPIO0_ISR1H@h	/* config GPIO input select */
 	ori	r3,r3,GPIO0_ISR1H@l
-	lis	r4,CFG_GPIO0_ISR1H@h
-	ori	r4,r4,CFG_GPIO0_ISR1H@l
+	lis	r4,CONFIG_SYS_GPIO0_ISR1H@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
 	stw	r4,0(r3)
 	lis	r3,GPIO0_ISR1L@h
 	ori	r3,r3,GPIO0_ISR1L@l
-	lis	r4,CFG_GPIO0_ISR1L@h
-	ori	r4,r4,CFG_GPIO0_ISR1L@l
+	lis	r4,CONFIG_SYS_GPIO0_ISR1L@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
 	stw	r4,0(r3)
 
 	lis	r3,GPIO0_TSRH@h		/* config GPIO three-state select */
 	ori	r3,r3,GPIO0_TSRH@l
-	lis	r4,CFG_GPIO0_TSRH@h
-	ori	r4,r4,CFG_GPIO0_TSRH@l
+	lis	r4,CONFIG_SYS_GPIO0_TSRH@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_TSRH@l
 	stw	r4,0(r3)
 	lis	r3,GPIO0_TSRL@h
 	ori	r3,r3,GPIO0_TSRL@l
-	lis	r4,CFG_GPIO0_TSRL@h
-	ori	r4,r4,CFG_GPIO0_TSRL@l
+	lis	r4,CONFIG_SYS_GPIO0_TSRL@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_TSRL@l
 	stw	r4,0(r3)
 
 	lis	r3,GPIO0_TCR@h		/* config GPIO driver output enables */
 	ori	r3,r3,GPIO0_TCR@l
-	lis	r4,CFG_GPIO0_TCR@h
-	ori	r4,r4,CFG_GPIO0_TCR@l
+	lis	r4,CONFIG_SYS_GPIO0_TCR@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_TCR@l
 	stw	r4,0(r3)
 
 	li	r3,pb1ap		/* program EBC bank 1 for RTC access */
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB1AP@h
-	ori	r3,r3,CFG_EBC_PB1AP@l
+	lis	r3,CONFIG_SYS_EBC_PB1AP@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB1AP@l
 	mtdcr	ebccfgd,r3
 	li	r3,pb1cr
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB1CR@h
-	ori	r3,r3,CFG_EBC_PB1CR@l
+	lis	r3,CONFIG_SYS_EBC_PB1CR@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB1CR@l
 	mtdcr	ebccfgd,r3
 
 	li	r3,pb1ap		/* program EBC bank 1 for RTC access */
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB1AP@h
-	ori	r3,r3,CFG_EBC_PB1AP@l
+	lis	r3,CONFIG_SYS_EBC_PB1AP@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB1AP@l
 	mtdcr	ebccfgd,r3
 	li	r3,pb1cr
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB1CR@h
-	ori	r3,r3,CFG_EBC_PB1CR@l
+	lis	r3,CONFIG_SYS_EBC_PB1CR@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB1CR@l
 	mtdcr	ebccfgd,r3
 
 	li	r3,pb4ap		/* program EBC bank 4 for FPGA access */
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB4AP@h
-	ori	r3,r3,CFG_EBC_PB4AP@l
+	lis	r3,CONFIG_SYS_EBC_PB4AP@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB4AP@l
 	mtdcr	ebccfgd,r3
 	li	r3,pb4cr
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB4CR@h
-	ori	r3,r3,CFG_EBC_PB4CR@l
+	lis	r3,CONFIG_SYS_EBC_PB4CR@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB4CR@l
 	mtdcr	ebccfgd,r3
 #endif
 
@@ -2111,20 +2131,20 @@ nand_boot_common:
 	 * First initialize SDRAM. It has to be available *before* calling
 	 * nand_boot().
 	 */
-	lis	r3,CFG_SDRAM_BASE@h
-	ori	r3,r3,CFG_SDRAM_BASE@l
+	lis	r3,CONFIG_SYS_SDRAM_BASE@h
+	ori	r3,r3,CONFIG_SYS_SDRAM_BASE@l
 	bl	initdram
 
 	/*
 	 * Now copy the 4k SPL code into SDRAM and continue execution
 	 * from there.
 	 */
-	lis	r3,CFG_NAND_BOOT_SPL_DST@h
-	ori	r3,r3,CFG_NAND_BOOT_SPL_DST@l
-	lis	r4,CFG_NAND_BOOT_SPL_SRC@h
-	ori	r4,r4,CFG_NAND_BOOT_SPL_SRC@l
-	lis	r5,CFG_NAND_BOOT_SPL_SIZE@h
-	ori	r5,r5,CFG_NAND_BOOT_SPL_SIZE@l
+	lis	r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
+	ori	r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
+	lis	r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
+	ori	r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
+	lis	r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
+	ori	r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
 	bl	nand_boot_relocate
 
 	/*
diff --git a/cpu/ppc4xx/usb.c b/cpu/ppc4xx/usb.c
index cb8d5c7..592efe7 100644
--- a/cpu/ppc4xx/usb.c
+++ b/cpu/ppc4xx/usb.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 
 #ifdef CONFIG_4xx_DCACHE
 #include <asm/mmu.h>
@@ -63,4 +63,4 @@ int usb_cpu_init_fail(void)
 	return 0;
 }
 
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index 5dbd842..2607ed6 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -660,7 +660,7 @@ static void td_fill (ohci_t *ohci, unsigned int info,
 	td->index = index;
 	td->data = (__u32)data;
 #ifdef OHCI_FILL_TRACE
-	if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
+	if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
 		for (i = 0; i < len; i++)
 		printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
 		printf("\n");
@@ -761,7 +761,7 @@ static void dl_transfer_length(td_t * td)
 	tdCBP  = ohci_cpu_to_le32 (td->hwCBP);
 
 
-	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+	if (!(usb_pipecontrol(lurb_priv->pipe) &&
 	    ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
 		if (tdBE != 0) {
 			if (td->hwCBP == 0)
@@ -1023,7 +1023,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 urb_priv.actual_length = 0;
 pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
 #endif
-	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+	if (usb_pipeint(pipe)) {
 		info("Root-Hub submit IRQ: NOT implemented");
 		return 0;
 	}
@@ -1248,7 +1248,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 
 	/* allow more time for a BULK device to react - some are slow */
 #define BULK_TO	 5000	/* timeout in milliseconds */
-	if (usb_pipetype (pipe) == PIPE_BULK)
+	if (usb_pipebulk(pipe))
 		timeout = BULK_TO;
 	else
 		timeout = 100;
@@ -1600,9 +1600,9 @@ int usb_lowlevel_init(void)
 	gohci.sleeping = 0;
 	gohci.irq = -1;
 #if defined(CONFIG_440EP)
-	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
-#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
-	gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
+	gohci.regs = (struct ohci_regs *)(CONFIG_SYS_PERIPHERAL_BASE | 0x1000);
+#elif defined(CONFIG_440EPX) || defined(CONFIG_SYS_USB_HOST)
+	gohci.regs = (struct ohci_regs *)(CONFIG_SYS_USB_HOST);
 #endif
 
 	gohci.flags = 0;
diff --git a/cpu/ppc4xx/usbdev.h b/cpu/ppc4xx/usbdev.h
index 3446d98..ef6a2da 100644
--- a/cpu/ppc4xx/usbdev.h
+++ b/cpu/ppc4xx/usbdev.h
@@ -1,31 +1,31 @@
 #include <config.h>
 
 /*Common Registers*/
-#define USB2D0_INTRIN_16   (CFG_USB_DEVICE | 0x100)
-#define USB2D0_POWER_8     (CFG_USB_DEVICE | 0x102)
-#define USB2D0_FADDR_8     (CFG_USB_DEVICE | 0x103)
-#define USB2D0_INTRINE_16  (CFG_USB_DEVICE | 0x104)
-#define USB2D0_INTROUT_16  (CFG_USB_DEVICE | 0x106)
-#define USB2D0_INTRUSBE_8  (CFG_USB_DEVICE | 0x108)
-#define USB2D0_INTRUSB_8   (CFG_USB_DEVICE | 0x109)
-#define USB2D0_INTROUTE_16 (CFG_USB_DEVICE | 0x10a)
-#define USB2D0_TSTMODE_8   (CFG_USB_DEVICE | 0x10c)
-#define USB2D0_INDEX_8     (CFG_USB_DEVICE | 0x10d)
-#define USB2D0_FRAME_16    (CFG_USB_DEVICE | 0x10e)
+#define USB2D0_INTRIN_16   (CONFIG_SYS_USB_DEVICE | 0x100)
+#define USB2D0_POWER_8     (CONFIG_SYS_USB_DEVICE | 0x102)
+#define USB2D0_FADDR_8     (CONFIG_SYS_USB_DEVICE | 0x103)
+#define USB2D0_INTRINE_16  (CONFIG_SYS_USB_DEVICE | 0x104)
+#define USB2D0_INTROUT_16  (CONFIG_SYS_USB_DEVICE | 0x106)
+#define USB2D0_INTRUSBE_8  (CONFIG_SYS_USB_DEVICE | 0x108)
+#define USB2D0_INTRUSB_8   (CONFIG_SYS_USB_DEVICE | 0x109)
+#define USB2D0_INTROUTE_16 (CONFIG_SYS_USB_DEVICE | 0x10a)
+#define USB2D0_TSTMODE_8   (CONFIG_SYS_USB_DEVICE | 0x10c)
+#define USB2D0_INDEX_8     (CONFIG_SYS_USB_DEVICE | 0x10d)
+#define USB2D0_FRAME_16    (CONFIG_SYS_USB_DEVICE | 0x10e)
 
 /*Indexed Registers*/
-#define USB2D0_INCSR0_8    (CFG_USB_DEVICE | 0x110)
-#define USB2D0_INCSR_16    (CFG_USB_DEVICE | 0x110)
-#define USB2D0_INMAXP_16   (CFG_USB_DEVICE | 0x112)
-#define USB2D0_OUTCSR_16   (CFG_USB_DEVICE | 0x114)
-#define USB2D0_OUTMAXP_16  (CFG_USB_DEVICE | 0x116)
-#define USB2D0_OUTCOUNT0_8 (CFG_USB_DEVICE | 0x11a)
-#define USB2D0_OUTCOUNT_16 (CFG_USB_DEVICE | 0x11a)
+#define USB2D0_INCSR0_8    (CONFIG_SYS_USB_DEVICE | 0x110)
+#define USB2D0_INCSR_16    (CONFIG_SYS_USB_DEVICE | 0x110)
+#define USB2D0_INMAXP_16   (CONFIG_SYS_USB_DEVICE | 0x112)
+#define USB2D0_OUTCSR_16   (CONFIG_SYS_USB_DEVICE | 0x114)
+#define USB2D0_OUTMAXP_16  (CONFIG_SYS_USB_DEVICE | 0x116)
+#define USB2D0_OUTCOUNT0_8 (CONFIG_SYS_USB_DEVICE | 0x11a)
+#define USB2D0_OUTCOUNT_16 (CONFIG_SYS_USB_DEVICE | 0x11a)
 
 /*FIFOs*/
-#define USB2D0_FIFO_0 (CFG_USB_DEVICE | 0x120)
-#define USB2D0_FIFO_1 (CFG_USB_DEVICE | 0x124)
-#define USB2D0_FIFO_2 (CFG_USB_DEVICE | 0x128)
-#define USB2D0_FIFO_3 (CFG_USB_DEVICE | 0x12c)
+#define USB2D0_FIFO_0 (CONFIG_SYS_USB_DEVICE | 0x120)
+#define USB2D0_FIFO_1 (CONFIG_SYS_USB_DEVICE | 0x124)
+#define USB2D0_FIFO_2 (CONFIG_SYS_USB_DEVICE | 0x128)
+#define USB2D0_FIFO_3 (CONFIG_SYS_USB_DEVICE | 0x12c)
 
 void usb_dev_init(void);