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| author | stroese <stroese> | 2003-02-10 16:26:37 +0000 |
|---|---|---|
| committer | stroese <stroese> | 2003-02-10 16:26:37 +0000 |
| commit | 6177445dabe5421bc4415236fc2a14d70821bdd1 (patch) | |
| tree | 17f5781ab2f5db0e0e12990484a73663ef89a4ca /cpu/ppc4xx | |
| parent | aacf9a49aa1a74d46726fbaee2b8e87e1dad6956 (diff) | |
| download | u-boot-imx-6177445dabe5421bc4415236fc2a14d70821bdd1.zip u-boot-imx-6177445dabe5421bc4415236fc2a14d70821bdd1.tar.gz u-boot-imx-6177445dabe5421bc4415236fc2a14d70821bdd1.tar.bz2 | |
Added 4MByte and 128MByte onboard SDRAM
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/sdram.c | 109 |
1 files changed, 105 insertions, 4 deletions
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index d64bf96..a77448e 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -35,13 +35,17 @@ #define MAGIC2 0x22222222 #define MAGIC3 0x33333333 #define MAGIC4 0x44444444 +#define MAGIC5 0x55555555 +#define MAGIC6 0x66666666 #define ADDR_ZERO 0x00000000 #define ADDR_400 0x00000400 +#define ADDR_01MB 0x00100000 #define ADDR_08MB 0x00800000 #define ADDR_16MB 0x01000000 #define ADDR_32MB 0x02000000 #define ADDR_64MB 0x04000000 +#define ADDR_128MB 0x08000000 #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) @@ -77,6 +81,59 @@ void sdram_init(void) } /* + * Set MB0CF for bank 0. (0-128MB) Address Mode 3 since 13x10(4) + */ + mtsdram0(mem_mb0cf, 0x000A4001); + + mtsdram0(mem_sdtr1, sdtr1); + mtsdram0(mem_rtr, rtr); + + /* + * Wait for 200us + */ + udelay(200); + + /* + * Set memory controller options reg, MCOPT1. + * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + * read/prefetch. + */ + mtsdram0(mem_mcopt1, 0x80800000); + + /* + * Wait for 10ms + */ + udelay(10000); + + /* + * Test if 128 MByte are equipped (mirror test) + */ + *(volatile ulong *)ADDR_ZERO = MAGIC0; + *(volatile ulong *)ADDR_08MB = MAGIC1; + *(volatile ulong *)ADDR_16MB = MAGIC2; + *(volatile ulong *)ADDR_32MB = MAGIC3; + *(volatile ulong *)ADDR_64MB = MAGIC4; + + if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) && + (*(volatile ulong *)ADDR_08MB == MAGIC1) && + (*(volatile ulong *)ADDR_16MB == MAGIC2) && + (*(volatile ulong *)ADDR_32MB == MAGIC3)) { + /* + * OK, 128MB detected -> all done + */ + return; + } + + /* + * Now test for 64 MByte... + */ + + /* + * Disable memory controller. + */ + mtsdram0(mem_mcopt1, 0x00000000); + + /* * Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) */ mtsdram0(mem_mb0cf, 0x00084001); @@ -117,11 +174,11 @@ void sdram_init(void) */ return; } - + /* * Now test for 32 MByte... */ - + /* * Disable memory controller. */ @@ -162,9 +219,8 @@ void sdram_init(void) } /* - * Setup for 16 MByte... + * Now test for 16 MByte... */ - /* * Disable memory controller. */ @@ -186,6 +242,51 @@ void sdram_init(void) * Wait for 10ms */ udelay(10000); + + /* + * Test if 16 MByte are equipped (mirror test) + */ + *(volatile ulong *)ADDR_ZERO = MAGIC0; + *(volatile ulong *)ADDR_400 = MAGIC1; + *(volatile ulong *)ADDR_01MB = MAGIC5; + *(volatile ulong *)ADDR_08MB = MAGIC2; +/* *(volatile ulong *)ADDR_16MB = MAGIC3;*/ + + if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) && + (*(volatile ulong *)ADDR_400 == MAGIC1) && + (*(volatile ulong *)ADDR_01MB == MAGIC5) && + (*(volatile ulong *)ADDR_08MB == MAGIC2)) { + /* + * OK, 16MB detected -> all done + */ + return; + } + + /* + * Setup for 4 MByte... + */ + + /* + * Disable memory controller. + */ + mtsdram0(mem_mcopt1, 0x00000000); + + /* + * Set MB0CF for bank 0. (0-4MB) Address Mode 5 since 11x8(2) + */ + mtsdram0(mem_mb0cf, 0x00008001); + + /* + * Set memory controller options reg, MCOPT1. + * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst + * read/prefetch. + */ + mtsdram0(mem_mcopt1, 0x80800000); + + /* + * Wait for 10ms + */ + udelay(10000); } #endif /* CONFIG_SDRAM_BANK0 */ |