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| author | Stefan Roese <sr@denx.de> | 2007-04-29 16:40:31 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-04-29 16:40:31 +0200 |
| commit | bd38b7ecfdf01e0b7bce551a0834226630be81c1 (patch) | |
| tree | e86a79fb7791af81a3325d0e177abdc2d97624d4 /cpu/ppc4xx | |
| parent | 6f69bbc8f33f03f6a1adf845101c15a9917ff5f5 (diff) | |
| parent | 14da5f7675bbb427c469e3f45006e027b6e21db9 (diff) | |
| download | u-boot-imx-bd38b7ecfdf01e0b7bce551a0834226630be81c1.zip u-boot-imx-bd38b7ecfdf01e0b7bce551a0834226630be81c1.tar.gz u-boot-imx-bd38b7ecfdf01e0b7bce551a0834226630be81c1.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 2 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 54 |
2 files changed, 28 insertions, 28 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index b56629b..2ecd3e4 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -1124,7 +1124,7 @@ static void program_codt(unsigned long *dimm_populated, modt3 = 0x00000000; } } - } else { + } else { codt |= SDRAM_CODT_DQS_2_5_V_DDR1; modt0 = 0x00000000; modt1 = 0x00000000; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3b1586c..a96083c 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1892,11 +1892,11 @@ pll_wait: #endif /* CONFIG_405EP */ #if defined(CONFIG_440) -#define function_prolog(func_name) .text; \ +#define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ func_name: -#define function_epilog(func_name) .type func_name,@function; \ +#define function_epilog(func_name) .type func_name,@function; \ .size func_name,.-func_name /*----------------------------------------------------------------------------+ @@ -1952,13 +1952,13 @@ pll_wait: +----------------------------------------------------------------------------*/ function_prolog(dcbz_area) rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 -..d_ra2:mtctr r5 -..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 +..d_ra2:mtctr r5 +..d_ag2:dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag2 sync blr function_epilog(dcbz_area) @@ -1967,26 +1967,26 @@ pll_wait: | dflush. Assume 32K at vector address is cachable. +----------------------------------------------------------------------------*/ function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 ..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 +..ag: dcbf r0,r3 + addi r3,r3,-32 + bdnz ..ag sync - mtmsr r9 + mtmsr r9 blr function_epilog(dflush) #endif /* CONFIG_440 */ |