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| author | wdenk <wdenk> | 2004-03-14 15:20:55 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-03-14 15:20:55 +0000 |
| commit | aaf224ab4ec400abefa17982cbd2ae995adc9978 (patch) | |
| tree | 68a329c03bf5b31851c26a7bc6f48e6931fd6c82 /cpu/ppc4xx | |
| parent | 3d3befa754fedb320f779320ac0ab11deb0a6275 (diff) | |
| download | u-boot-imx-aaf224ab4ec400abefa17982cbd2ae995adc9978.zip u-boot-imx-aaf224ab4ec400abefa17982cbd2ae995adc9978.tar.gz u-boot-imx-aaf224ab4ec400abefa17982cbd2ae995adc9978.tar.bz2 | |
* Patch by Stephan Linz, 09 Mar 2004
- Add support for the SSV ADNP/ESC1 (Nios Softcore)
* Patch by George G. Davis, 9 Mar 2004:
fix recent build failure for SA1100 target
* Patch by Travis Sawyer, 09 Mar 2004:
Support native interrupt mode for the IBM440GX.
Previously it was running in 440GP compatibility mode.
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/interrupts.c | 29 |
1 files changed, 23 insertions, 6 deletions
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 71052b4..7fa2f77 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -170,9 +170,21 @@ int interrupt_init_cpu (unsigned *decrementer_count) #endif #if defined(CONFIG_440_GX) + /* Take the GX out of compatibility mode + * Travis Sawyer, 9 Mar 2004 + * NOTE: 440gx user manual inconsistency here + * Compatibility mode and Ethernet Clock select are not + * correct in the manual + */ + mfsdr(sdr_mfr, val); + val &= ~0x10000000; + mtsdr(sdr_mfr,val); + /* Enable UIC interrupts via UIC Base Enable Register */ - mtdcr(uicb0er, UICB0_ALL); - mtdcr(uicb0cr, UICB0_ALL); + mtdcr(uicb0sr, UICB0_ALL); + mtdcr(uicb0er, 0x54000000); + /* None are critical */ + mtdcr(uicb0cr, 0); #endif return (0); @@ -194,11 +206,16 @@ void external_interrupt(struct pt_regs *regs) /* 440 GX uses base uic register */ uic_msr = mfdcr(uicb0msr); - uic0_interrupt(0); - uic1_interrupt(0); - uic2_interrupt(0); + if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) ) + uic0_interrupt(0); - mtdcr(uicb0sr, UICB0_ALL); + if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) + uic1_interrupt(0); + + if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) + uic2_interrupt(0); + + mtdcr(uicb0sr, uic_msr); return; |