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authorDave Mitchell <dmitch71@gmail.com>2008-11-20 14:09:50 -0600
committerStefan Roese <sr@denx.de>2008-11-21 11:02:04 +0100
commitddf45cc758d394591fb9bcdcbe96530f733f2bce (patch)
tree661e05764bd4978aef056a431da33377dfa3a389 /cpu/ppc4xx
parentb14ca4b61a681f75f3125676e09d7ce6af66e927 (diff)
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ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
-rw-r--r--cpu/ppc4xx/start.S27
1 files changed, 20 insertions, 7 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index db34e84..e68cf9b 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -678,9 +678,12 @@ _start:
/* not all PPC's have internal SRAM usable as L2-cache */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ lis r1, 0x0000
+ ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
+ mtdcr L2_CACHE_CFG,r1
#endif
lis r2,0x7fff
@@ -705,8 +708,8 @@ _start:
lis r1, 0x8003
ori r1,r1, 0x0980 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440SPE)
- lis r1,0x0000 /* BAS = 0000_0000 */
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ lis r1,0x0000 /* BAS = X_0000_0000 */
ori r1,r1,0x0984 /* first 64k */
mtdcr ISRAM0_SB0CR,r1
lis r1,0x0001
@@ -718,10 +721,20 @@ _start:
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr ISRAM0_SB3CR,r1
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- lis r1,0x4000 /* BAS = 8000_0000 */
- ori r1,r1,0x4580 /* 16k */
- mtdcr ISRAM0_SB0CR,r1
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+ lis r2,0x7fff
+ ori r2,r2,0xffff
+ mfdcr r1,ISRAM1_DPC
+ and r1,r1,r2 /* Disable parity check */
+ mtdcr ISRAM1_DPC,r1
+ mfdcr r1,ISRAM1_PMEG
+ and r1,r1,r2 /* Disable pwr mgmt */
+ mtdcr ISRAM1_PMEG,r1
+
+ lis r1,0x0004 /* BAS = 4_0004_0000 */
+ ori r1,r1,0x0984 /* 64k */
+ mtdcr ISRAM1_SB0CR,r1
+#endif
#elif defined(CONFIG_460SX)
lis r1,0x0000 /* BAS = 0000_0000 */
ori r1,r1,0x0B84 /* first 128k */