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| author | Dave Mitchell <dmitch71@gmail.com> | 2008-11-20 14:00:49 -0600 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-11-21 10:52:33 +0100 |
| commit | b14ca4b61a681f75f3125676e09d7ce6af66e927 (patch) | |
| tree | 64bdc03bfd8407ef9116c6b7a7afa80a0c2a373f /cpu/ppc4xx | |
| parent | 711e2b2af820d21d9931d4cf8057d3894600fd54 (diff) | |
| download | u-boot-imx-b14ca4b61a681f75f3125676e09d7ce6af66e927.zip u-boot-imx-b14ca4b61a681f75f3125676e09d7ce6af66e927.tar.gz u-boot-imx-b14ca4b61a681f75f3125676e09d7ce6af66e927.tar.bz2 | |
ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.
Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/start.S | 41 |
1 files changed, 21 insertions, 20 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 84d7a28..db34e84 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -72,6 +72,7 @@ #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/ppc4xx-isram.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" @@ -679,65 +680,65 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_460SX) - mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ + mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ #endif lis r2,0x7fff ori r2,r2,0xffff - mfdcr r1,isram0_dpc + mfdcr r1,ISRAM0_DPC and r1,r1,r2 /* Disable parity check */ - mtdcr isram0_dpc,r1 - mfdcr r1,isram0_pmeg + mtdcr ISRAM0_DPC,r1 + mfdcr r1,ISRAM0_PMEG and r1,r1,r2 /* Disable pwr mgmt */ - mtdcr isram0_pmeg,r1 + mtdcr ISRAM0_PMEG,r1 lis r1,0x8000 /* BAS = 8000_0000 */ #if defined(CONFIG_440GX) || defined(CONFIG_440SP) ori r1,r1,0x0980 /* first 64k */ - mtdcr isram0_sb0cr,r1 + mtdcr ISRAM0_SB0CR,r1 lis r1,0x8001 ori r1,r1,0x0980 /* second 64k */ - mtdcr isram0_sb1cr,r1 + mtdcr ISRAM0_SB1CR,r1 lis r1, 0x8002 ori r1,r1, 0x0980 /* third 64k */ - mtdcr isram0_sb2cr,r1 + mtdcr ISRAM0_SB2CR,r1 lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ - mtdcr isram0_sb3cr,r1 + mtdcr ISRAM0_SB3CR,r1 #elif defined(CONFIG_440SPE) lis r1,0x0000 /* BAS = 0000_0000 */ ori r1,r1,0x0984 /* first 64k */ - mtdcr isram0_sb0cr,r1 + mtdcr ISRAM0_SB0CR,r1 lis r1,0x0001 ori r1,r1,0x0984 /* second 64k */ - mtdcr isram0_sb1cr,r1 + mtdcr ISRAM0_SB1CR,r1 lis r1, 0x0002 ori r1,r1, 0x0984 /* third 64k */ - mtdcr isram0_sb2cr,r1 + mtdcr ISRAM0_SB2CR,r1 lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ - mtdcr isram0_sb3cr,r1 + mtdcr ISRAM0_SB3CR,r1 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r1,0x4000 /* BAS = 8000_0000 */ ori r1,r1,0x4580 /* 16k */ - mtdcr isram0_sb0cr,r1 + mtdcr ISRAM0_SB0CR,r1 #elif defined(CONFIG_460SX) lis r1,0x0000 /* BAS = 0000_0000 */ ori r1,r1,0x0B84 /* first 128k */ - mtdcr isram0_sb0cr,r1 + mtdcr ISRAM0_SB0CR,r1 lis r1,0x0001 ori r1,r1,0x0B84 /* second 128k */ - mtdcr isram0_sb1cr,r1 + mtdcr ISRAM0_SB1CR,r1 lis r1, 0x0002 ori r1,r1, 0x0B84 /* third 128k */ - mtdcr isram0_sb2cr,r1 + mtdcr ISRAM0_SB2CR,r1 lis r1, 0x0003 ori r1,r1, 0x0B84 /* fourth 128k */ - mtdcr isram0_sb3cr,r1 + mtdcr ISRAM0_SB3CR,r1 #elif defined(CONFIG_440GP) ori r1,r1,0x0380 /* 8k rw */ - mtdcr isram0_sb0cr,r1 - mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ + mtdcr ISRAM0_SB0CR,r1 + mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ #endif #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ |