diff options
| author | Stefan Roese <sr@denx.de> | 2007-11-16 14:16:54 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-11-16 14:16:54 +0100 |
| commit | f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03 (patch) | |
| tree | 8af96c3ac5e48e17b0f4595f5cd53f8eabef3204 /cpu/ppc4xx | |
| parent | ecdcbd4f8c1f8cefd785752f4e7536aae2a4ecf9 (diff) | |
| download | u-boot-imx-f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03.zip u-boot-imx-f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03.tar.gz u-boot-imx-f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03.tar.bz2 | |
ppc4xx: Enable 405EX PCIe UTL register configuration
Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/4xx_pcie.c | 44 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu.c | 2 |
2 files changed, 42 insertions, 4 deletions
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index de79552..cafd933 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -401,6 +401,48 @@ int ppc4xx_init_pcie(void) return 0; } #else +static void ppc4xx_setup_utl(u32 port) +{ + u32 utl_base; + + /* + * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xfffffc01); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xfffffc01); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); + + break; + } + utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE; + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000); + out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000); + out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066); + + out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c); + out_be32((u32 *)(utl_base + PEUTL_RCSTA), + in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000); +} + int ppc4xx_init_pcie(void) { /* @@ -643,14 +685,12 @@ int ppc4xx_init_pcie_port(int port, int rootport) return -1; } -#if defined(CONFIG_440SPE) /* * Setup UTL registers - but only on revA! * We use default settings for revB chip. */ if (!ppc440spe_revB()) ppc4xx_setup_utl(port); -#endif /* * We map PCI Express configuration access into the 512MB regions diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index d376f52..9e9c685 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -510,7 +510,6 @@ int checkcpu (void) return 0; } -#if defined (CONFIG_440SPE) int ppc440spe_revB() { unsigned int pvr; @@ -520,7 +519,6 @@ int ppc440spe_revB() { else return 0; } -#endif /* ------------------------------------------------------------------------- */ |