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| author | Rafal Jaworowski <raj@semihalf.com> | 2007-07-31 18:19:54 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-02 08:25:18 +0200 |
| commit | dec99558b9ea75a37940d07f41a3565a50b54ad1 (patch) | |
| tree | 5ce95a3ed9f5ee894892e85774dcf8f945ef31e7 /cpu/ppc4xx | |
| parent | d2f68006627eda6cb6c7f364bddf621dbfd2fc68 (diff) | |
| download | u-boot-imx-dec99558b9ea75a37940d07f41a3565a50b54ad1.zip u-boot-imx-dec99558b9ea75a37940d07f41a3565a50b54ad1.tar.gz u-boot-imx-dec99558b9ea75a37940d07f41a3565a50b54ad1.tar.bz2 | |
[ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A
This brings back separate settings for PCIe bus numbers depending on chip
revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa
commit. 440SPe rev. A does NOT work properly with the same settings as for
the rev. B (no devices are seen on the bus during enumeration).
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/440spe_pcie.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index d6c4be5..7b27e87 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -783,9 +783,14 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) /* * Set bus numbers on our root port */ - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + if (ppc440spe_revB()) { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + } else { + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); + } /* * Set up outbound translation to hose->mem_space from PLB |