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authorStefan Roese <sr@denx.de>2008-09-10 16:53:47 +0200
committerStefan Roese <sr@denx.de>2008-09-12 07:12:33 +0200
commit7bf5ecfa50722a9feb45ea8f04da75f5d406f20b (patch)
treea28ce7747e214469fa77199f4ea83ba8e2965e48 /cpu/ppc4xx
parent61737c59a3285f6fadf96a5836879898c04ec28d (diff)
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ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports
This patch fixes a problem introdiced with patch bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by initdram()]. The boards affected are: - PCI405 - PPChameleonEVB - quad100hd - taihu - zeus Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
-rw-r--r--cpu/ppc4xx/sdram.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 7d60ad6..b5a6a4c 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -209,15 +209,15 @@ phys_size_t initdram(int board_type)
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+ phys_size_t size = mb0cf[i].size;
+
/*
* OK, size detected. Enable second bank if
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
- u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
-
mtsdram(mem_mcopt1, 0x00000000);
- mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
+ mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
mtsdram(mem_mcopt1, 0x80800000);
udelay(10000);
@@ -230,13 +230,19 @@ phys_size_t initdram(int board_type)
mb0cf[i].size) {
mtsdram(mem_mb1cf, 0);
mtsdram(mem_mcopt1, 0);
+ } else {
+ /*
+ * We have two identical banks, so the size
+ * is twice the bank size
+ */
+ size = 2 * size;
}
#endif
/*
* OK, size detected -> all done
*/
- return mb0cf[i].size;
+ return size;
}
}