Merge git://git.denx.de/u-boot into x1

Conflicts:

	drivers/usb/usb_ohci.c

25 files changed, 544 insertions, 521 deletions

diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index b21b13e..57861b3 100644
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -52,12 +52,12 @@
 /*
  * Set default values
  */
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED	50000
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED	50000
 #endif
 
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE	0xFE
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE	0xFE
 #endif
 
 #define ONE_BILLION	1000000000
@@ -163,7 +163,7 @@ long int spd_sdram(int(read_spd)(uint addr))
 		 * Make sure I2C controller is initialized
 		 * before continuing.
 		 */
-		i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	}
 
 	/* Make shure we are using SDRAM */
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index 9efcede..153391e 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -62,12 +62,12 @@
 /*
  * Set default values
  */
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED	50000
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED	50000
 #endif
 
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE	0xFE
+#ifndef CONFIG_SYS_I2C_SLAVE
+#define CONFIG_SYS_I2C_SLAVE	0xFE
 #endif
 
 #define ONE_BILLION	1000000000
@@ -119,7 +119,7 @@ struct bank_param {
 
 typedef struct bank_param BANKPARMS;
 
-#ifdef CFG_SIMULATE_SPD_EEPROM
+#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
 extern const unsigned char cfg_simulate_spd_eeprom[128];
 #endif
 
@@ -174,7 +174,7 @@ long int spd_sdram(void) {
 	 * Make sure I2C controller is initialized
 	 * before continuing.
 	 */
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/*
 	 * Read the SPD information using I2C interface. Check to see if the
@@ -265,7 +265,7 @@ long int spd_sdram(void) {
 	/*
 	 * If ecc is enabled, initialize the parity bits.
 	 */
-	ecc_init(CFG_SDRAM_BASE, total_size);
+	ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
 #endif
 
 	return total_size;
@@ -275,14 +275,14 @@ static unsigned char spd_read(uchar chip, uint addr)
 {
 	unsigned char data[2];
 
-#ifdef CFG_SIMULATE_SPD_EEPROM
-	if (chip == CFG_SIMULATE_SPD_EEPROM) {
+#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
+	if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
 		/*
 		 * Onboard spd eeprom requested -> simulate values
 		 */
 		return cfg_simulate_spd_eeprom[addr];
 	}
-#endif /* CFG_SIMULATE_SPD_EEPROM */
+#endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
 
 	if (i2c_probe(chip) == 0) {
 		if (i2c_read(chip, addr, 1, data, 1) == 0) {
@@ -1120,7 +1120,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
 	/*
 	 * reset the bank_base address
 	 */
-	bank_base_addr = CFG_SDRAM_BASE;
+	bank_base_addr = CONFIG_SYS_SDRAM_BASE;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		if (dimm_populated[dimm_num] == TRUE) {
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index f1d7684..4544b78 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -402,8 +402,8 @@ phys_size_t initdram(int board_type)
 	 */
 
 	/* switch to correct I2C bus */
-	I2C_SET_BUS(CFG_SPD_BUS_NUM);
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/*------------------------------------------------------------------
 	 * Clear out the serial presence detect buffers.
@@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	/*
 	 * Set optimal value for Memory Queue HB/LL Configuration registers
 	 */
-	mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
-	      SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
-	mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
-	      SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+	mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
+	      SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
+	      SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
+	mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
+	      SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
+	      SDRAM_CONF1LL_RPLM);
 	mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
 #endif
 }
@@ -2976,62 +2978,62 @@ phys_size_t initdram(int board_type)
 
 	/* Set Memory Bank Configuration Registers */
 
-	mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
-	mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
-	mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
-	mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+	mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
+	mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
+	mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
+	mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
 
 	/* Set Memory Clock Timing Register */
 
-	mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+	mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
 
 	/* Set Refresh Time Register */
 
-	mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
+	mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
 
 	/* Set SDRAM Timing Registers */
 
-	mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
-	mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
-	mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+	mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
+	mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
+	mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
 
 	/* Set Mode and Extended Mode Registers */
 
-	mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
-	mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+	mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
+	mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
 
 	/* Set Memory Controller Options 1 Register */
 
-	mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+	mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
 
 	/* Set Manual Initialization Control Registers */
 
-	mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
-	mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
-	mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
-	mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
-	mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
-	mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
-	mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
-	mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
-	mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
-	mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
-	mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
-	mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
-	mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
-	mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
-	mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
-	mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+	mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
+	mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
+	mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
+	mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
+	mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
+	mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
+	mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
+	mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
+	mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
+	mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
+	mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
+	mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
+	mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
+	mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
+	mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
+	mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
 
 	/* Set On-Die Termination Registers */
 
-	mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
-	mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
-	mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+	mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
+	mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
+	mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
 
 	/* Set Write Timing Register */
 
-	mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
+	mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
 
 	/*
 	 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
@@ -3052,12 +3054,12 @@ phys_size_t initdram(int board_type)
 
 	/* Set Delay Control Registers */
 
-	mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
+	mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
 
 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
-	mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
-	mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
-	mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
+	mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
+	mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
+	mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
 	/*
@@ -3077,7 +3079,7 @@ phys_size_t initdram(int board_type)
 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
 
 #if defined(CONFIG_DDR_ECC)
-	ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+	ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
 #endif /* defined(CONFIG_DDR_ECC) */
 
 	ppc4xx_ibm_ddr2_register_dump();
@@ -3093,7 +3095,7 @@ phys_size_t initdram(int board_type)
 
 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 
-	return (CFG_MBYTES_SDRAM << 20);
+	return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }
 #endif /* CONFIG_SPD_EEPROM */
 
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 6d4d043..d7b16da 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -225,7 +225,7 @@
  * Some boards do not have a PHY for each ethernet port. These ports
  * are known as Fixed PHY (or PHY-less) ports. For such ports, set
  * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
- * then define CFG_FIXED_PHY_PORTS to define what the speed and
+ * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
  * duplex should be for these ports in the board configuration
  * file.
  *
@@ -237,20 +237,20 @@
  *     #define CONFIG_PHY2_ADDR   CONFIG_FIXED_PHY
  *     #define CONFIG_PHY3_ADDR   3
  *
- *     #define CFG_FIXED_PHY_PORT(devnum,speed,duplex) \
+ *     #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
  *                     {devnum, speed, duplex},
  *
- *     #define CFG_FIXED_PHY_PORTS \
- *                     CFG_FIXED_PHY_PORT(0,1000,FULL) \
- *                     CFG_FIXED_PHY_PORT(2,100,HALF)
+ *     #define CONFIG_SYS_FIXED_PHY_PORTS \
+ *                     CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
+ *                     CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
  */
 
 #ifndef CONFIG_FIXED_PHY
 #define CONFIG_FIXED_PHY	0xFFFFFFFF /* Fixed PHY (PHY-less) */
 #endif
 
-#ifndef CFG_FIXED_PHY_PORTS
-#define CFG_FIXED_PHY_PORTS	/* default is an empty array */
+#ifndef CONFIG_SYS_FIXED_PHY_PORTS
+#define CONFIG_SYS_FIXED_PHY_PORTS	/* default is an empty array */
 #endif
 
 struct fixed_phy_port {
@@ -260,7 +260,7 @@ struct fixed_phy_port {
 };
 
 static const struct fixed_phy_port fixed_phy_port[] = {
-	CFG_FIXED_PHY_PORTS	/* defined in board configuration file */
+	CONFIG_SYS_FIXED_PHY_PORTS	/* defined in board configuration file */
 };
 
 /*-----------------------------------------------------------------------------+
@@ -1337,8 +1337,8 @@ get_speed:
 #ifdef CONFIG_4xx_DCACHE
 		flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
 		if (!last_used_ea)
-#if defined(CFG_MEM_TOP_HIDE)
-			bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE;
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+			bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
 #else
 			bd_uncached = bis->bi_memsize;
 #endif
diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 83b9883..1e3e20d 100644
--- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -53,11 +53,11 @@
 #define MAXBXCF			4
 #define SDRAM_RXBAS_SHIFT_1M	20
 
-#if defined(CFG_DECREMENT_PATTERNS)
+#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
 #define NUMMEMTESTS		24
 #else
 #define NUMMEMTESTS		8
-#endif /* CFG_DECREMENT_PATTERNS */
+#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
 #define NUMLOOPS		1	/* configure as you deem approporiate */
 #define NUMMEMWORDS		16
 
@@ -174,6 +174,23 @@ static inline void ecc_clear_status_reg(void)
 #endif
 }
 
+/*
+ * Reset and relock memory DLL after SDRAM_CLKTR change
+ */
+static inline void relock_memory_DLL(void)
+{
+	u32 reg;
+
+	mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
+
+	do {
+		mfsdram(SDRAM_MCSTAT, reg);
+	} while (!(reg & SDRAM_MCSTAT_MIC_COMP));
+
+	mfsdram(SDRAM_MCOPT2, reg);
+	mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
+}
+
 static int ecc_check_status_reg(void)
 {
 	u32 ecc_status;
@@ -237,7 +254,7 @@ static int short_mem_test(u32 *base_address)
 		 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 		 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55},
 
-#if defined(CFG_DECREMENT_PATTERNS)
+#if defined(CONFIG_SYS_DECREMENT_PATTERNS)
 	/* 8 */	{0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 		 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 		 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
@@ -302,7 +319,7 @@ static int short_mem_test(u32 *base_address)
 		 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
 		 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0,
 		 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0},
-#endif /* CFG_DECREMENT_PATTERNS */
+#endif /* CONFIG_SYS_DECREMENT_PATTERNS */
 								 };
 
 	mfsdram(SDRAM_MCOPT1, ecc_mode);
@@ -981,6 +998,8 @@ u32 DQS_autocalibration(void)
 
 		mtsdram(SDRAM_CLKTR, clkp << 30);
 
+		relock_memory_DLL();
+
 		putc('\b');
 		putc(slash[loopi++ % 8]);
 
@@ -1170,6 +1189,8 @@ u32 DQS_autocalibration(void)
 
 		mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
 
+		relock_memory_DLL();
+
 		mfsdram(SDRAM_RQDC, rqdc_reg);
 		rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
 		mtsdram(SDRAM_RQDC, rqdc_reg |
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index c28c7ac..eca92e8 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -108,12 +108,12 @@ void pci_405gp_init(struct pci_controller *hose)
 	bd_t *bd = gd->bd;
 
 	unsigned short temp_short;
-	unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
+	unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
 	char *ptmla_str, *ptmms_str;
 #endif
-	unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
-	unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
+	unsigned long ptmla[2]    = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
+	unsigned long ptmms[2]    = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
 	unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
 	unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
@@ -268,22 +268,22 @@ void pci_405gp_init(struct pci_controller *hose)
 	/*
 	 * Insert Subsystem Vendor and Device ID
 	 */
-	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 #ifdef CONFIG_CPCI405
 	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
-		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 	else
-		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
+		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
 #else
-	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 #endif
 
 	/*
 	 * Insert Class-code
 	 */
-#ifdef CFG_PCI_CLASSCODE
-	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
-#endif /* CFG_PCI_CLASSCODE */
+#ifdef CONFIG_SYS_PCI_CLASSCODE
+	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
+#endif /* CONFIG_SYS_PCI_CLASSCODE */
 
 	/*--------------------------------------------------------------------------+
 	 * If PCI speed = 66Mhz, set 66Mhz capable bit.
@@ -405,8 +405,8 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
  */
 static struct pci_config_table pci_405gp_config_table[] = {
 /*if VendID is 0 it terminates the table search (ie Walnut)*/
-#ifdef CFG_PCI_SUBSYS_VENDORID
-	{CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
+#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
+	{CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 #endif
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
@@ -488,10 +488,10 @@ int pci_440_init (struct pci_controller *hose)
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + reg_num++,
-		       CFG_PCI_TARGBASE,
-		       CFG_PCI_MEMBASE,
-#ifdef CFG_PCI_MEMSIZE
-		       CFG_PCI_MEMSIZE,
+		       CONFIG_SYS_PCI_TARGBASE,
+		       CONFIG_SYS_PCI_MEMBASE,
+#ifdef CONFIG_SYS_PCI_MEMSIZE
+		       CONFIG_SYS_PCI_MEMSIZE,
 #else
 		       0x10000000,
 #endif
@@ -523,11 +523,11 @@ int pci_440_init (struct pci_controller *hose)
 	/*--------------------------------------------------------------------------+
 	 * PCI target init
 	 *--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_SYS_PCI_TARGET_INIT)
 	pci_target_init(hose);                /* Let board setup pci target */
 #else
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
 	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
@@ -542,9 +542,9 @@ int pci_440_init (struct pci_controller *hose)
 
 	/*--------------------------------------------------------------------------+
 	 * PCI master init: default is one 256MB region for PCI memory:
-	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CFG_PCI_MEMBASE
+	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CONFIG_SYS_PCI_MEMBASE
 	 *--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_SYS_PCI_MASTER_INIT)
 	pci_master_init(hose);          /* Let board setup pci master */
 #else
 	out32r( PCIX0_POM0SA, 0 ); /* disable */
@@ -558,7 +558,7 @@ int pci_440_init (struct pci_controller *hose)
 	out32r( PCIX0_POM0LAL, 0x00000000 );
 	out32r( PCIX0_POM0LAH, 0x00000003 );
 #endif
-	out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
+	out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
 	out32r( PCIX0_POM0PCIAH, 0x00000000 );
 	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
 	out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 0aadc06..fd40d8a 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -49,12 +49,12 @@ enum {
 
 static int validate_endpoint(struct pci_controller *hose)
 {
-	if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
+	if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE)
 		return (is_end_point(0));
-	else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
+	else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE)
 		return (is_end_point(1));
-#if CFG_PCIE_NR_PORTS > 2
-	else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
+	else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE)
 		return (is_end_point(2));
 #endif
 
@@ -67,13 +67,13 @@ static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
 
 	/* use local configuration space for the first bus */
 	if (PCI_BUS(devfn) == 0) {
-		if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
-			base = (u8*)CFG_PCIE0_XCFGBASE;
-		if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
-			base = (u8*)CFG_PCIE1_XCFGBASE;
-#if CFG_PCIE_NR_PORTS > 2
-		if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
-			base = (u8*)CFG_PCIE2_XCFGBASE;
+		if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE)
+			base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE;
+		if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE)
+			base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE;
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
+		if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE)
+			base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE;
 #endif
 	}
 
@@ -86,7 +86,7 @@ static void pcie_dmer_disable(void)
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA);
 	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE),
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA);
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE),
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA);
 #endif
@@ -98,7 +98,7 @@ static void pcie_dmer_enable(void)
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA);
 	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE),
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA);
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE),
 		mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
 #endif
@@ -286,7 +286,7 @@ static void ppc4xx_setup_utl(u32 port) {
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
 		break;
 	}
-	utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+	utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
 
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
@@ -412,21 +412,21 @@ static void ppc4xx_setup_utl(u32 port)
 	 */
 	switch (port) {
 	case 0:
-		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE));
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE));
 		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);	/* BAM 11100000=4KB */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
 		break;
 
 	case 1:
-		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE));
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE)
+		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE));
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)
 			+ 0x1000);
 		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);	/* BAM 11100000=4KB */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
 		break;
 	}
-	utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+	utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port);
 
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
@@ -512,20 +512,20 @@ static void ppc4xx_setup_utl(u32 port)
 	switch (port) {
 	case 0:
 		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE);
 		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
 		break;
 
 	case 1:
 		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
-		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
+		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE);
 		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
 		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
 
 		break;
 	}
-	utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
+	utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE;
 
 	/*
 	 * Set buffer allocations and then assert VRB and TXE.
@@ -761,9 +761,9 @@ static inline u64 ppc4xx_get_cfgaddr(int port)
 {
 #if defined(CONFIG_405EX)
 	if (port == 0)
-		return (u64)CFG_PCIE0_CFGBASE;
+		return (u64)CONFIG_SYS_PCIE0_CFGBASE;
 	else
-		return (u64)CFG_PCIE1_CFGBASE;
+		return (u64)CONFIG_SYS_PCIE1_CFGBASE;
 #endif
 #if defined(CONFIG_440SPE)
 	if (ppc440spe_revB()) {
@@ -895,7 +895,7 @@ int ppc4xx_init_pcie_port(int port, int rootport)
 		mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low);
 		mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
 		break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
 		mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high);
 		mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low);
@@ -947,20 +947,20 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 
 	switch (port) {
 	case 0:
-		mbase = (u32 *)CFG_PCIE0_XCFGBASE;
-		rmbase = (u32 *)CFG_PCIE0_CFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
+		rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
 		break;
 	case 1:
-		mbase = (u32 *)CFG_PCIE1_XCFGBASE;
-		rmbase = (u32 *)CFG_PCIE1_CFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
+		rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
 		break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
-		mbase = (u32 *)CFG_PCIE2_XCFGBASE;
-		rmbase = (u32 *)CFG_PCIE2_CFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
+		rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
 		break;
 #endif
 	}
@@ -979,19 +979,19 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 	 * subregions and to enable the outbound translation.
 	 */
 	out_le32(mbase + PECFG_POM0LAH, 0x00000000);
-	out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE +
-		 port * CFG_PCIE_MEMSIZE);
+	out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE +
+		 port * CONFIG_SYS_PCIE_MEMSIZE);
 	debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH),
 	      in_le32(mbase + PECFG_POM0LAL));
 
 	switch (port) {
 	case 0:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
 		      mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)),
 		      mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)),
@@ -999,26 +999,26 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 		      mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0)));
 		break;
 	case 1:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
 		      mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)),
 		      mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)),
 		      mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)),
 		      mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1)));
 		break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n",
 		      mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)),
 		      mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)),
@@ -1072,17 +1072,17 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 
 	switch (port) {
 	case 0:
-		mbase = (u32 *)CFG_PCIE0_XCFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
 		break;
 	case 1:
-		mbase = (u32 *)CFG_PCIE1_XCFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
 		break;
-#if defined(CFG_PCIE2_CFGBASE)
+#if defined(CONFIG_SYS_PCIE2_CFGBASE)
 	case 2:
-		mbase = (u32 *)CFG_PCIE2_XCFGBASE;
-		hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+		mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
+		hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
 		break;
 #endif
 	}
@@ -1098,29 +1098,29 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 
 	switch (port) {
 	case 0:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		break;
 	case 1:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		break;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
 	case 2:
-		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH);
-		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE +
-		      port * CFG_PCIE_MEMSIZE);
+		mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH);
+		mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE +
+		      port * CONFIG_SYS_PCIE_MEMSIZE);
 		mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
 		mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
-		      ~(CFG_PCIE_MEMSIZE - 1) | 3);
+		      ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3);
 		break;
 #endif
 	}
@@ -1141,8 +1141,8 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port)
 	out_le32(mbase + PECFG_BAR2HMPA, 0);
 	out_le32(mbase + PECFG_BAR2LMPA, 0);
 
-	out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE));
-	out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE));
+	out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE));
+	out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE));
 	out_le32(mbase + PECFG_PIMEN, 0x1);
 
 	/* Enable I/O, Mem, and Busmaster cycles */
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index 766e586..c106ac2 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -66,20 +66,20 @@ DECLARE_GLOBAL_DATA_PTR;
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART0_BASE	(CFG_PERIPHERAL_BASE + 0x00000300)
-#define UART1_BASE	(CFG_PERIPHERAL_BASE + 0x00000400)
+#define UART0_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
+#define UART1_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
 #else
-#define UART0_BASE	(CFG_PERIPHERAL_BASE + 0x00000200)
-#define UART1_BASE	(CFG_PERIPHERAL_BASE + 0x00000300)
+#define UART0_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
+#define UART1_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
 #endif
 
 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE	(CFG_PERIPHERAL_BASE + 0x00000600)
+#define UART2_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
 #endif
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART2_BASE	(CFG_PERIPHERAL_BASE + 0x00000500)
-#define UART3_BASE	(CFG_PERIPHERAL_BASE + 0x00000600)
+#define UART2_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
+#define UART3_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
 #endif
 
 #if defined(CONFIG_440GP)
@@ -147,7 +147,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ACTING_UART1_BASE	UART1_BASE
 #endif
 
-#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
+#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 #error "External serial clock not supported on AMCC PPC405EP!"
 #endif
 
@@ -199,8 +199,8 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
 	/* Correct UART frequency in bd-info struct now that
 	 * the UART divisor is available
 	 */
-#ifdef CFG_EXT_SERIAL_CLOCK
-	gd->uart_clk = CFG_EXT_SERIAL_CLOCK;
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+	gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 #else
 	gd->uart_clk = sys_info.freqUART / udiv;
 #endif
@@ -218,7 +218,7 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
 }
 
 #if (defined(CONFIG_440) || defined(CONFIG_405EX)) &&	\
-    !defined(CFG_EXT_SERIAL_CLOCK)
+    !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 static void serial_divs (int baudrate, unsigned long *pudiv,
 			 unsigned short *pbdiv)
 {
@@ -315,7 +315,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
 	mtcpr(cprperd0, reg);
 	*pbdiv = div / udiv;
 }
-#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
+#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
 
 /*
  * Minimal serial functions needed to use one of the SMC ports
@@ -328,18 +328,18 @@ int serial_init_dev(unsigned long base)
 	unsigned long reg;
 	unsigned long udiv;
 	unsigned short bdiv;
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	unsigned long tmp;
 #endif
 
 	MFREG(UART0_SDR, reg);
 	reg &= ~CR0_MASK;
 
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
 	tmp  = gd->baudrate * 16;
-	bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+	bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
 #else
 	/* For 440, the cpu clock is on divider chain A, UART on divider
 	 * chain B ... so cpu clock is irrelevant. Get the "optimized"
@@ -384,11 +384,11 @@ int serial_init_dev (unsigned long base)
 	clk = tmp = 0;
 	mfsdr(UART0_SDR, reg);
 	reg &= ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
 	tmp  = gd->baudrate * 16;
-	bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+	bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
 #else
 	serial_divs(gd->baudrate, &udiv, &bdiv);
 #endif
@@ -411,7 +411,7 @@ int serial_init_dev (unsigned long base)
 #ifdef CONFIG_405EP
 	reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
 	clk = gd->cpu_clk;
-	tmp = CFG_BASE_BAUD * 16;
+	tmp = CONFIG_SYS_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
 	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 		udiv = UDIV_MAX;
@@ -420,16 +420,16 @@ int serial_init_dev (unsigned long base)
 	mtdcr (cpc0_ucr, reg);
 #else /* CONFIG_405EP */
 	reg = mfdcr(cntrl0) & ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
-	clk = CFG_EXT_SERIAL_CLOCK;
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 	udiv = 1;
 	reg |= CR0_EXTCLK_ENA;
 #else
 	clk = gd->cpu_clk;
-#ifdef CFG_405_UART_ERRATA_59
+#ifdef CONFIG_SYS_405_UART_ERRATA_59
 	udiv = 31;			/* Errata 59: stuck at 31 */
 #else
-	tmp = CFG_BASE_BAUD * 16;
+	tmp = CONFIG_SYS_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
 	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 		udiv = UDIV_MAX;
diff --git a/cpu/ppc4xx/cache.S b/cpu/ppc4xx/cache.S
index ceb3ec0..269716f 100644
--- a/cpu/ppc4xx/cache.S
+++ b/cpu/ppc4xx/cache.S
@@ -143,8 +143,8 @@ _GLOBAL(flush_dcache)
 _GLOBAL(invalidate_dcache)
 	addi	r6,0,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
-	lis	r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha	/* TBS for large sized cache */
-	ori	r7,r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
+	lis	r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha	/* TBS for large sized cache */
+	ori	r7,r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
 					/* NOTE: dccci invalidates both */
 	mtctr	r7			/* ways in the D cache */
 ..dcloop:
diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c
index 8b2954c..a1696d3 100644
--- a/cpu/ppc4xx/commproc.c
+++ b/cpu/ppc4xx/commproc.c
@@ -30,10 +30,10 @@
 
 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 
-#if defined(CFG_POST_WORD_ADDR)
-# define _POST_ADDR	((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR))
-#elif defined(CFG_POST_ALT_WORD_ADDR)
-# define _POST_ADDR	(CFG_POST_ALT_WORD_ADDR)
+#if defined(CONFIG_SYS_POST_WORD_ADDR)
+# define _POST_ADDR	((CONFIG_SYS_OCM_DATA_ADDR) + (CONFIG_SYS_POST_WORD_ADDR))
+#elif defined(CONFIG_SYS_POST_ALT_WORD_ADDR)
+# define _POST_ADDR	(CONFIG_SYS_POST_ALT_WORD_ADDR)
 #endif
 
 void post_word_store (ulong a)
@@ -57,7 +57,7 @@ ulong post_word_load (void)
 void bootcount_store (ulong a)
 {
 	volatile ulong *save_addr =
-		(volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR);
+		(volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
 
 	save_addr[0] = a;
 	save_addr[1] = BOOTCOUNT_MAGIC;
@@ -66,7 +66,7 @@ void bootcount_store (ulong a)
 ulong bootcount_load (void)
 {
 	volatile ulong *save_addr =
-		(volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR);
+		(volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR);
 
 	if (save_addr[1] != BOOTCOUNT_MAGIC)
 		return 0;
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index bc9335a..66a7737 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -629,14 +629,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_BOARD_RESET)
 	board_reset();
 #else
-#if defined(CFG_4xx_RESET_TYPE)
-	mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
+#if defined(CONFIG_SYS_4xx_RESET_TYPE)
+	mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
 #else
 	/*
 	 * Initiate system reset in debug control register DBCR
 	 */
 	mtspr(dbcr0, 0x30000000);
-#endif /* defined(CFG_4xx_RESET_TYPE) */
+#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
 #endif /* defined(CONFIG_BOARD_RESET) */
 
 	return 1;
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index dee9807..b5d81f2 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -32,8 +32,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-#ifndef CFG_PLL_RECONFIG
-#define CFG_PLL_RECONFIG	0
+#ifndef CONFIG_SYS_PLL_RECONFIG
+#define CONFIG_SYS_PLL_RECONFIG	0
 #endif
 
 void reconfigure_pll(u32 new_cpu_freq)
@@ -142,32 +142,32 @@ cpu_init_f (void)
 	u32 val;
 #endif
 
-	reconfigure_pll(CFG_PLL_RECONFIG);
+	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 
-#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
+#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
-#if defined(CFG_GPIO0_OR)
-	out32(GPIO0_OR, CFG_GPIO0_OR);		/* set initial state of output pins	*/
+#if defined(CONFIG_SYS_GPIO0_OR)
+	out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR);		/* set initial state of output pins	*/
 #endif
-#if defined(CFG_GPIO0_ODR)
-	out32(GPIO0_ODR, CFG_GPIO0_ODR);	/* open-drain select			*/
+#if defined(CONFIG_SYS_GPIO0_ODR)
+	out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);	/* open-drain select			*/
 #endif
-	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select			*/
-	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select				*/
-	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select			*/
-	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-#if defined(CFG_GPIO0_ISR2H)
-	out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
-	out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
+	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select			*/
+	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
+	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select				*/
+	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
+	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select			*/
+	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
+#if defined(CONFIG_SYS_GPIO0_ISR2H)
+	out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
+	out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
 #endif
-#if defined (CFG_GPIO0_TCR)
-	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/
+#if defined (CONFIG_SYS_GPIO0_TCR)
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);	/* enable output driver for outputs	*/
 #endif
-#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
 
 #if defined (CONFIG_405EP)
 	/*
@@ -181,14 +181,14 @@ cpu_init_f (void)
 	mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
 #endif /* CONFIG_405EP */
 
-#if defined(CFG_4xx_GPIO_TABLE)
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
 	gpio_set_chip_configuration();
-#endif /* CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
 
 	/*
 	 * External Bus Controller (EBC) Setup
 	 */
-#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
      defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
      defined(CONFIG_405EX) || defined(CONFIG_405))
@@ -209,47 +209,47 @@ cpu_init_f (void)
 	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
 #endif
 
-	mtebc(pb0ap, CFG_EBC_PB0AP);
-	mtebc(pb0cr, CFG_EBC_PB0CR);
+	mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
+	mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
 #endif
 
-#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
-	mtebc(pb1ap, CFG_EBC_PB1AP);
-	mtebc(pb1cr, CFG_EBC_PB1CR);
+#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
+	mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP);
+	mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR);
 #endif
 
-#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
-	mtebc(pb2ap, CFG_EBC_PB2AP);
-	mtebc(pb2cr, CFG_EBC_PB2CR);
+#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
+	mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP);
+	mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR);
 #endif
 
-#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
-	mtebc(pb3ap, CFG_EBC_PB3AP);
-	mtebc(pb3cr, CFG_EBC_PB3CR);
+#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
+	mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP);
+	mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
 #endif
 
-#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
-	mtebc(pb4ap, CFG_EBC_PB4AP);
-	mtebc(pb4cr, CFG_EBC_PB4CR);
+#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
+	mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP);
+	mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR);
 #endif
 
-#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
-	mtebc(pb5ap, CFG_EBC_PB5AP);
-	mtebc(pb5cr, CFG_EBC_PB5CR);
+#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
+	mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP);
+	mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR);
 #endif
 
-#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
-	mtebc(pb6ap, CFG_EBC_PB6AP);
-	mtebc(pb6cr, CFG_EBC_PB6CR);
+#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
+	mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP);
+	mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR);
 #endif
 
-#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
-	mtebc(pb7ap, CFG_EBC_PB7AP);
-	mtebc(pb7cr, CFG_EBC_PB7CR);
+#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
+	mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP);
+	mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR);
 #endif
 
-#if defined (CFG_EBC_CFG)
-	mtebc(EBC0_CFG, CFG_EBC_CFG);
+#if defined (CONFIG_SYS_EBC_CFG)
+	mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
 #endif
 
 #if defined(CONFIG_WATCHDOG)
@@ -261,9 +261,9 @@ cpu_init_f (void)
 #else
 	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
 #endif
-#if defined(CFG_4xx_RESET_TYPE)
+#if defined(CONFIG_SYS_4xx_RESET_TYPE)
 	val &= ~0x30000000;			/* clear WRC bits */
-	val |= CFG_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
+	val |= CONFIG_SYS_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
 #endif
 	mtspr(tcr, val);
 
diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c
index 967e61b..ffc3817 100644
--- a/cpu/ppc4xx/denali_data_eye.c
+++ b/cpu/ppc4xx/denali_data_eye.c
@@ -127,7 +127,7 @@ void denali_core_search_data_eye(void)
 		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55
 	};
 
-	ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
+	ram_pointer = (volatile u32 *)(CONFIG_SYS_SDRAM_BASE);
 
 	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
 		/* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 670fc5c..4705e21 100644
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -1048,8 +1048,8 @@ phys_size_t initdram(int board_type)
 	 * before continuing.
 	 */
 	/* switch to correct I2C bus */
-	I2C_SET_BUS(CFG_SPD_BUS_NUM);
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/*------------------------------------------------------------------
 	 * Clear out the serial presence detect buffers.
@@ -1185,27 +1185,27 @@ phys_size_t initdram(int board_type)
 	 * Map the first 1 MiB of memory in the TLB, and perform the data eye
 	 * search.
 	 */
-	program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
 	denali_core_search_data_eye();
 	denali_sdram_register_dump();
-	remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE);
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
 #endif
 
 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
-	program_tlb(0, CFG_SDRAM_BASE, dram_size, 0);
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
 	sync();
 	/* Zero the memory */
 	debug("Zeroing SDRAM...");
-#if defined(CFG_MEM_TOP_HIDE)
-	dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE);
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+	dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
 #else
-#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
+#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
 #endif
 	/* Write modified dcache lines back to memory */
-	clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
+	clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
 	debug("Completed\n");
 	sync();
-	remove_tlb(CFG_SDRAM_BASE, dram_size);
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
 
 #if defined(CONFIG_DDR_ECC)
 	/*
@@ -1236,7 +1236,7 @@ phys_size_t initdram(int board_type)
 #endif /* defined(CONFIG_DDR_ECC) */
 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
 
-	program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
 	return dram_size;
 }
 
diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c
index a2eb07b..3f989e7 100644
--- a/cpu/ppc4xx/ecc.c
+++ b/cpu/ppc4xx/ecc.c
@@ -68,7 +68,7 @@
  *
  *  Output(s):
  *    start - A pointer to the start of memory covered by ECC with
- *	      CFG_ECC_PATTERN written to all locations and ECC data
+ *	      CONFIG_SYS_ECC_PATTERN written to all locations and ECC data
  *	      primed.
  *
  *  Returns:
@@ -76,7 +76,7 @@
  */
 void ecc_init(unsigned long * const start, unsigned long size)
 {
-	const unsigned long pattern = CFG_ECC_PATTERN;
+	const unsigned long pattern = CONFIG_SYS_ECC_PATTERN;
 	unsigned long * const end = (unsigned long * const)((long)start + size);
 	unsigned long * current = start;
 	unsigned long mcopt1;
diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h
index aecf291..67c3bff 100644
--- a/cpu/ppc4xx/ecc.h
+++ b/cpu/ppc4xx/ecc.h
@@ -33,9 +33,9 @@
 #ifndef _ECC_H_
 #define _ECC_H_
 
-#if !defined(CFG_ECC_PATTERN)
-#define	CFG_ECC_PATTERN	0x00000000
-#endif /* !defined(CFG_ECC_PATTERN) */
+#if !defined(CONFIG_SYS_ECC_PATTERN)
+#define	CONFIG_SYS_ECC_PATTERN	0x00000000
+#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */
 
 /*
  * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c
index df99f53..c0d351a 100644
--- a/cpu/ppc4xx/gpio.c
+++ b/cpu/ppc4xx/gpio.c
@@ -26,8 +26,8 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
-#if defined(CFG_4xx_GPIO_TABLE)
-gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
+gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE;
 #endif
 
 #if defined(GPIO0_OSRL)
@@ -132,7 +132,7 @@ int gpio_read_in_bit(int pin)
 	return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
 }
 
-#if defined(CFG_4xx_GPIO_TABLE)
+#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
 void gpio_set_chip_configuration(void)
 {
 	unsigned char i=0, j=0, offs=0, gpio_core;
@@ -252,4 +252,4 @@ void gpio_set_chip_configuration(void)
 		}
 	}
 }
-#endif /* CFG_4xx_GPIO_TABLE */
+#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index d8be2ce..0deb149 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -42,8 +42,8 @@ DECLARE_GLOBAL_DATA_PTR;
  * runs from ROM, and we can't switch buses because we can't modify
  * the global variables.
  */
-#ifdef CFG_SPD_BUS_NUM
-static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
+#ifdef CONFIG_SYS_SPD_BUS_NUM
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CONFIG_SYS_SPD_BUS_NUM;
 #else
 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
 #endif
@@ -95,14 +95,14 @@ void i2c_init(int speed, int slaveadd)
 	int val, divisor;
 	int bus;
 
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
 	/* call board specific i2c bus reset routine before accessing the   */
 	/* environment, which might be in a chip on that bus. For details   */
 	/* about this problem see doc/I2C_Edge_Conditions.                  */
 	i2c_init_board();
 #endif
 
-	for (bus = 0; bus < CFG_MAX_I2C_BUS; bus++) {
+	for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
 		I2C_SET_BUS(bus);
 
 		/* Handle possible failed I2C state */
@@ -161,7 +161,7 @@ void i2c_init(int speed, int slaveadd)
 	}
 
 	/* set to SPD bus as default bus upon powerup */
-	I2C_SET_BUS(CFG_SPD_BUS_NUM);
+	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 }
 
 /*
@@ -361,7 +361,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
 	}
 
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 	/*
 	 * EEPROM chips that implement "address overflow" are ones
 	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -374,7 +374,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
 	 * hidden in the chip address.
 	 */
 	if (alen > 0)
-		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 	if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
 		if (gd->have_console)
@@ -401,7 +401,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
 		xaddr[3] = addr & 0xFF;
 	}
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 	/*
 	 * EEPROM chips that implement "address overflow" are ones
 	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -414,7 +414,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
 	 * hidden in the chip address.
 	 */
 	if (alen > 0)
-		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 
 	return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
@@ -451,7 +451,7 @@ unsigned int i2c_get_bus_num(void)
 
 int i2c_set_bus_num(unsigned int bus)
 {
-	if (bus >= CFG_MAX_I2C_BUS)
+	if (bus >= CONFIG_SYS_MAX_I2C_BUS)
 		return -1;
 
 	i2c_bus_num = bus;
@@ -463,12 +463,12 @@ int i2c_set_bus_num(unsigned int bus)
 /* TODO: add 100/400k switching */
 unsigned int i2c_get_bus_speed(void)
 {
-	return CFG_I2C_SPEED;
+	return CONFIG_SYS_I2C_SPEED;
 }
 
 int i2c_set_bus_speed(unsigned int speed)
 {
-	if (speed != CFG_I2C_SPEED)
+	if (speed != CONFIG_SYS_I2C_SPEED)
 		return -1;
 
 	return 0;
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 7d96e79..3a5af12 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -149,8 +149,8 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 }
 #endif /* #ifndef CONFIG_NAND_SPL */
 
-#ifndef CFG_NAND_BCR
-#define CFG_NAND_BCR 0x80002222
+#ifndef CONFIG_SYS_NAND_BCR
+#define CONFIG_SYS_NAND_BCR 0x80002222
 #endif
 
 void board_nand_select_device(struct nand_chip *nand, int chip)
@@ -165,7 +165,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
 	/* Set NandFlash Core Configuration Register */
 	/* 1 col x 2 rows */
 	out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
-	out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CFG_NAND_BCR);
+	out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
 }
 
 static void ndfc_select_chip(struct mtd_info *mtd, int chip)
@@ -214,8 +214,8 @@ int board_nand_init(struct nand_chip *nand)
 	 */
 	mtebc(EBC0_CFG, 0xb8400000);
 
-	mtebc(pb0cr, CFG_EBC_PB0CR);
-	mtebc(pb0ap, CFG_EBC_PB0AP);
+	mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
+	mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
 #endif
 
 	chip++;
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index b5a6a4c..6d5f8d6 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -37,7 +37,7 @@
 
 #ifndef CONFIG_440
 
-#ifndef CFG_SDRAM_TABLE
+#ifndef CONFIG_SYS_SDRAM_TABLE
 sdram_conf_t mb0cf[] = {
 	{(128 << 20), 13, 0x000A4001},	    /* (0-128MB) Address Mode 3, 13x10(4) */
 	{(64 << 20),  13, 0x00084001},	    /* (0-64MB) Address Mode 3, 13x9(4)	  */
@@ -46,72 +46,72 @@ sdram_conf_t mb0cf[] = {
 	{(4 << 20),   11, 0x00008001},	    /* (0-4MB) Address Mode 5, 11x8(2)	  */
 };
 #else
-sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 #endif
 
 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
 
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
 static ulong ns2clks(ulong ns)
 {
 	ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
 
 	return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
 }
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
 
 static ulong compute_sdtr1(ulong speed)
 {
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
 	ulong tmp;
 	ulong sdtr1 = 0;
 
 	/* CASL */
-	if (CFG_SDRAM_CASL < 2)
+	if (CONFIG_SYS_SDRAM_CASL < 2)
 		sdtr1 |= (1 << SDRAM0_TR_CASL);
 	else
-		if (CFG_SDRAM_CASL > 4)
+		if (CONFIG_SYS_SDRAM_CASL > 4)
 			sdtr1 |= (3 << SDRAM0_TR_CASL);
 		else
-			sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL);
+			sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
 
 	/* PTA */
-	tmp = ns2clks(CFG_SDRAM_PTA);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
 	if ((tmp >= 2) && (tmp <= 4))
 		sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
 	else
 		sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
 
 	/* CTP */
-	tmp = ns2clks(CFG_SDRAM_CTP);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
 	if ((tmp >= 2) && (tmp <= 4))
 		sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
 	else
 		sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
 
 	/* LDF */
-	tmp = ns2clks(CFG_SDRAM_LDF);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
 	if ((tmp >= 2) && (tmp <= 4))
 		sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
 	else
 		sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
 
 	/* RFTA */
-	tmp = ns2clks(CFG_SDRAM_RFTA);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
 	if ((tmp >= 4) && (tmp <= 10))
 		sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
 	else
 		sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
 
 	/* RCD */
-	tmp = ns2clks(CFG_SDRAM_RCD);
+	tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
 	if ((tmp >= 2) && (tmp <= 4))
 		sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
 	else
 		sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
 
 	return sdtr1;
-#else /* CFG_SDRAM_CASL */
+#else /* CONFIG_SYS_SDRAM_CASL */
 	/*
 	 * If no values are configured in the board config file
 	 * use the default values, which seem to be ok for most
@@ -133,20 +133,20 @@ static ulong compute_sdtr1(ulong speed)
 		 */
 		return 0x0086400d;
 	}
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
 }
 
 /* refresh is expressed in ms */
 static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 {
-#ifdef CFG_SDRAM_CASL
+#ifdef CONFIG_SYS_SDRAM_CASL
 	ulong tmp;
 
 	tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
 	tmp /= 1000000;
 
 	return ((tmp & 0x00003FF8) << 16);
-#else /* CFG_SDRAM_CASL */
+#else /* CONFIG_SYS_SDRAM_CASL */
 	if (speed > 100000000) {
 		/*
 		 * 133 MHz SDRAM
@@ -158,7 +158,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 		 */
 		return 0x05f00000;
 	}
-#endif /* CFG_SDRAM_CASL */
+#endif /* CONFIG_SYS_SDRAM_CASL */
 }
 
 /*
@@ -256,17 +256,17 @@ phys_size_t initdram(int board_type)
  * board config file.
  */
 
-#ifndef CFG_SDRAM_TABLE
+#ifndef CONFIG_SYS_SDRAM_TABLE
 sdram_conf_t mb0cf[] = {
 	{(256 << 20), 13, 0x000C4001},	/* 256MB mode 3, 13x10(4)	*/
 	{(64 << 20),  12, 0x00082001}	/* 64MB mode 2, 12x9(4)		*/
 };
 #else
-sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 #endif
 
-#ifndef CFG_SDRAM0_TR0
-#define	CFG_SDRAM0_TR0		0x41094012
+#ifndef CONFIG_SYS_SDRAM0_TR0
+#define	CONFIG_SYS_SDRAM0_TR0		0x41094012
 #endif
 
 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
@@ -385,7 +385,7 @@ phys_size_t initdram(int board_type)
 		 * Following for CAS Latency = 2.5 @ 133 MHz PLB
 		 */
 		mtsdram(mem_b0cr, mb0cf[i].reg);
-		mtsdram(mem_tr0, CFG_SDRAM0_TR0);
+		mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
 		mtsdram(mem_tr1, 0x80800800);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
 		mtsdram(mem_rtr, 0x04100000);	/* Interval 7.8µs @ 133MHz PLB	*/
 		mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM*/
diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h
index 4fb9b1a..bea3376 100644
--- a/cpu/ppc4xx/sdram.h
+++ b/cpu/ppc4xx/sdram.h
@@ -47,19 +47,19 @@ typedef struct sdram_conf_s sdram_conf_t;
 #define SDRAM0_TR_RFTA		(31 - 29)
 #define SDRAM0_TR_RCD		(31 - 31)
 
-#ifdef CFG_SDRAM_CL
+#ifdef CONFIG_SYS_SDRAM_CL
 /* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */
-#define CFG_SDRAM_CASL		CFG_SDRAM_CL
-#define CFG_SDRAM_PTA		CFG_SDRAM_tRP
-#define CFG_SDRAM_CTP		(CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP)
-#define CFG_SDRAM_LDF		0
-#ifdef CFG_SDRAM_tRFC
-#define CFG_SDRAM_RFTA		CFG_SDRAM_tRFC
+#define CONFIG_SYS_SDRAM_CASL		CONFIG_SYS_SDRAM_CL
+#define CONFIG_SYS_SDRAM_PTA		CONFIG_SYS_SDRAM_tRP
+#define CONFIG_SYS_SDRAM_CTP		(CONFIG_SYS_SDRAM_tRC - CONFIG_SYS_SDRAM_tRCD - CONFIG_SYS_SDRAM_tRP)
+#define CONFIG_SYS_SDRAM_LDF		0
+#ifdef CONFIG_SYS_SDRAM_tRFC
+#define CONFIG_SYS_SDRAM_RFTA		CONFIG_SYS_SDRAM_tRFC
 #else
-#define CFG_SDRAM_RFTA		CFG_SDRAM_tRC
+#define CONFIG_SYS_SDRAM_RFTA		CONFIG_SYS_SDRAM_tRC
 #endif
-#define CFG_SDRAM_RCD		CFG_SDRAM_tRCD
-#endif /* #ifdef CFG_SDRAM_CL */
+#define CONFIG_SYS_SDRAM_RCD		CONFIG_SYS_SDRAM_tRCD
+#endif /* #ifdef CONFIG_SYS_SDRAM_CL */
 
 /*
  * Some defines for the 440 DDR controller
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 97411bd..31902a0 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -77,69 +77,69 @@
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-#ifdef CFG_INIT_DCACHE_CS
-# if (CFG_INIT_DCACHE_CS == 0)
+#ifdef CONFIG_SYS_INIT_DCACHE_CS
+# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
 #  define PBxAP pb0ap
 #  define PBxCR pb0cr
-#  if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
-#   define PBxAP_VAL CFG_EBC_PB0AP
-#   define PBxCR_VAL CFG_EBC_PB0CR
+#  if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 1)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 1)
 #  define PBxAP pb1ap
 #  define PBxCR pb1cr
-#  if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
-#   define PBxAP_VAL CFG_EBC_PB1AP
-#   define PBxCR_VAL CFG_EBC_PB1CR
+#  if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 2)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 2)
 #  define PBxAP pb2ap
 #  define PBxCR pb2cr
-#  if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
-#   define PBxAP_VAL CFG_EBC_PB2AP
-#   define PBxCR_VAL CFG_EBC_PB2CR
+#  if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 3)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 3)
 #  define PBxAP pb3ap
 #  define PBxCR pb3cr
-#  if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
-#   define PBxAP_VAL CFG_EBC_PB3AP
-#   define PBxCR_VAL CFG_EBC_PB3CR
+#  if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 4)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 4)
 #  define PBxAP pb4ap
 #  define PBxCR pb4cr
-#  if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
-#   define PBxAP_VAL CFG_EBC_PB4AP
-#   define PBxCR_VAL CFG_EBC_PB4CR
+#  if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 5)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 5)
 #  define PBxAP pb5ap
 #  define PBxCR pb5cr
-#  if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
-#   define PBxAP_VAL CFG_EBC_PB5AP
-#   define PBxCR_VAL CFG_EBC_PB5CR
+#  if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 6)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 6)
 #  define PBxAP pb6ap
 #  define PBxCR pb6cr
-#  if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
-#   define PBxAP_VAL CFG_EBC_PB6AP
-#   define PBxCR_VAL CFG_EBC_PB6CR
+#  if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
 #  endif
 # endif
-# if (CFG_INIT_DCACHE_CS == 7)
+# if (CONFIG_SYS_INIT_DCACHE_CS == 7)
 #  define PBxAP pb7ap
 #  define PBxCR pb7cr
-#  if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
-#   define PBxAP_VAL CFG_EBC_PB7AP
-#   define PBxCR_VAL CFG_EBC_PB7CR
+#  if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
+#   define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
+#   define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
 #  endif
 # endif
 # ifndef PBxAP_VAL
@@ -149,11 +149,11 @@
 #  define PBxCR_VAL	0
 # endif
 /*
- * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB
+ * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
  * used as temporary stack pointer for the primordial stack
  */
-# ifndef CFG_INIT_DCACHE_PBxAR
-#  define CFG_INIT_DCACHE_PBxAR	(EBC_BXAP_BME_DISABLED			| \
+# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
+#  define CONFIG_SYS_INIT_DCACHE_PBxAR	(EBC_BXAP_BME_DISABLED			| \
 				 EBC_BXAP_TWT_ENCODE(7)			| \
 				 EBC_BXAP_BCE_DISABLE			| \
 				 EBC_BXAP_BCT_2TRANS			| \
@@ -166,42 +166,42 @@
 				 EBC_BXAP_SOR_NONDELAYED		| \
 				 EBC_BXAP_BEM_WRITEONLY			| \
 				 EBC_BXAP_PEN_DISABLED)
-# endif /* CFG_INIT_DCACHE_PBxAR */
-# ifndef CFG_INIT_DCACHE_PBxCR
-#  define CFG_INIT_DCACHE_PBxCR	(EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR)	| \
+# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
+# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
+#  define CONFIG_SYS_INIT_DCACHE_PBxCR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR)	| \
 				 EBC_BXCR_BS_64MB			| \
 				 EBC_BXCR_BU_RW				| \
 				 EBC_BXCR_BW_16BIT)
-# endif /* CFG_INIT_DCACHE_PBxCR */
-# ifndef CFG_INIT_RAM_PATTERN
-#  define CFG_INIT_RAM_PATTERN	0xDEADDEAD
+# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
+# ifndef CONFIG_SYS_INIT_RAM_PATTERN
+#  define CONFIG_SYS_INIT_RAM_PATTERN	0xDEADDEAD
 # endif
-#endif /* CFG_INIT_DCACHE_CS */
+#endif /* CONFIG_SYS_INIT_DCACHE_CS */
 
-#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
-#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
+#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
+#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
 #endif
 
 /*
  * Unless otherwise overriden, enable two 128MB cachable instruction regions
- * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering
- * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions.
+ * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
+ * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
  */
-#if !defined(CFG_FLASH_BASE)
+#if !defined(CONFIG_SYS_FLASH_BASE)
 /* If not already defined, set it to the "last" 128MByte region */
-# define CFG_FLASH_BASE		0xf8000000
+# define CONFIG_SYS_FLASH_BASE		0xf8000000
 #endif
-#if !defined(CFG_ICACHE_SACR_VALUE)
-# define CFG_ICACHE_SACR_VALUE		\
-		(PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (  0 << 20)) | \
-		 PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \
-		 PPC_128MB_SACR_VALUE(CFG_FLASH_BASE))
-#endif /* !defined(CFG_ICACHE_SACR_VALUE) */
-
-#if !defined(CFG_DCACHE_SACR_VALUE)
-# define CFG_DCACHE_SACR_VALUE		\
+#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
+# define CONFIG_SYS_ICACHE_SACR_VALUE		\
+		(PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (  0 << 20)) | \
+		 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
+		 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
+#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
+
+#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
+# define CONFIG_SYS_DCACHE_SACR_VALUE		\
 		(0x00000000)
-#endif /* !defined(CFG_DCACHE_SACR_VALUE) */
+#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
 
 #define function_prolog(func_name)	.text; \
 					.align 2; \
@@ -609,15 +609,15 @@ _start:
 
 	/*----------------------------------------------------------------*/
 	/* Debug setup -- some (not very good) ice's need an event*/
-	/* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
+	/* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
 	/* value you need in this case 0x8cff 0000 should do the trick */
 	/*----------------------------------------------------------------*/
-#if defined(CFG_INIT_DBCR)
+#if defined(CONFIG_SYS_INIT_DBCR)
 	lis	r1,0xffff
 	ori	r1,r1,0xffff
 	mtspr	dbsr,r1			/* Clear all status bits */
-	lis	r0,CFG_INIT_DBCR@h
-	ori	r0,r0,CFG_INIT_DBCR@l
+	lis	r0,CONFIG_SYS_INIT_DBCR@h
+	ori	r0,r0,CONFIG_SYS_INIT_DBCR@l
 	mtspr	dbcr0,r0
 	isync
 #endif
@@ -627,12 +627,12 @@ _start:
 	/*----------------------------------------------------------------*/
 	li	r0,0
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* Clear Dcache to use as RAM */
-	addis	r3,r0,CFG_INIT_RAM_ADDR@h
-	ori	r3,r3,CFG_INIT_RAM_ADDR@l
-	addis	r4,r0,CFG_INIT_RAM_END@h
-	ori	r4,r4,CFG_INIT_RAM_END@l
+	addis	r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
+	addis	r4,r0,CONFIG_SYS_INIT_RAM_END@h
+	ori	r4,r4,CONFIG_SYS_INIT_RAM_END@l
 	rlwinm. r5,r4,0,27,31
 	rlwinm	r5,r4,27,5,31
 	beq	..d_ran
@@ -670,7 +670,7 @@ _start:
 	mtspr	dtv3,r1
 	msync
 	isync
-#endif /* CFG_INIT_RAM_DCACHE */
+#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 
 	/* 440EP & 440GR are only 440er PPC's without internal SRAM */
 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
@@ -744,8 +744,8 @@ _start:
 	/*----------------------------------------------------------------*/
 	/* Setup the stack in internal SRAM */
 	/*----------------------------------------------------------------*/
-	lis	r1,CFG_INIT_RAM_ADDR@h
-	ori	r1,r1,CFG_INIT_SP_OFFSET@l
+	lis	r1,CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
 	li	r0,0
 	stwu	r0,-4(r1)
 	stwu	r0,-4(r1)		/* Terminate call chain */
@@ -852,18 +852,18 @@ _start:
 	sync
 
 	/* Set-up icache cacheability. */
-	lis	r1, CFG_ICACHE_SACR_VALUE@h
-	ori	r1, r1, CFG_ICACHE_SACR_VALUE@l
+	lis	r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
+	ori	r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
 	mticcr	r1
 	isync
 
 	/* Set-up dcache cacheability. */
-	lis	r1, CFG_DCACHE_SACR_VALUE@h
-	ori	r1, r1, CFG_DCACHE_SACR_VALUE@l
+	lis	r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
+	ori	r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
 	mtdccr	r1
 
-	addis	r1,r0,CFG_INIT_RAM_ADDR@h
-	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
+	addis	r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
 	li	r0, 0			/* Make room for stack frame header and */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
@@ -908,31 +908,31 @@ _start:
 	bl	invalidate_dcache
 
 	/* Set-up icache cacheability. */
-	lis	r4, CFG_ICACHE_SACR_VALUE@h
-	ori	r4, r4, CFG_ICACHE_SACR_VALUE@l
+	lis	r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
+	ori	r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
 	mticcr	r4
 	isync
 
 	/* Set-up dcache cacheability. */
-	lis	r4, CFG_DCACHE_SACR_VALUE@h
-	ori	r4, r4, CFG_DCACHE_SACR_VALUE@l
+	lis	r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
+	ori	r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
 	mtdccr	r4
 
-#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
 	/*----------------------------------------------------------------------- */
 	/* Tune the speed and size for flash CS0  */
 	/*----------------------------------------------------------------------- */
 	bl	ext_bus_cntlr_init
 #endif
 
-#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
+#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
 	/*
 	 * For boards that don't have OCM and can't use the data cache
 	 * for their primordial stack, setup stack here directly after the
 	 * SDRAM is initialized in ext_bus_cntlr_init.
 	 */
-	lis	r1, CFG_INIT_RAM_ADDR@h
-	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
+	lis	r1, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
 
 	li	r0, 0			/* Make room for stack frame header and */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
@@ -946,7 +946,7 @@ _start:
 	ori	r0, r0, RESET_VECTOR@l
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
-#endif /* !(CFG_INIT_DCACHE_CS	|| !CFG_TEM_STACK_OCM) */
+#endif /* !(CONFIG_SYS_INIT_DCACHE_CS	|| !CONFIG_SYS_TEM_STACK_OCM) */
 
 #if defined(CONFIG_405EP)
 	/*----------------------------------------------------------------------- */
@@ -959,25 +959,25 @@ _start:
 	bl	ppc405ep_init		/* do ppc405ep specific init */
 #endif /* CONFIG_405EP */
 
-#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
+#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
 #if defined(CONFIG_405EZ)
 	/********************************************************************
 	 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
 	 *******************************************************************/
 	/*
 	 * We can map the OCM on the PLB3, so map it at
-	 * CFG_OCM_DATA_ADDR + 0x8000
+	 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
 	 */
-	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
-	ori	r3,r3,CFG_OCM_DATA_ADDR@l
+	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
+	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
 	mtdcr	ocmplb3cr1,r3		/* Set PLB Access */
 	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
 	mtdcr	ocmplb3cr2,r3		/* Set PLB Access */
 	isync
 
-	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
-	ori	r3,r3,CFG_OCM_DATA_ADDR@l
+	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
+	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 	ori	r3,r3,0x0270		/* 16K for Bank 1, R/W/Enable */
 	mtdcr	ocmdscr1, r3		/* Set Data Side */
 	mtdcr	ocmiscr1, r3		/* Set Instruction Side */
@@ -1003,8 +1003,8 @@ _start:
 	mtdcr	ocmdscntl, r4		/* set data-side IRAM config */
 	isync
 
-	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
-	ori	r3,r3,CFG_OCM_DATA_ADDR@l
+	lis	r3,CONFIG_SYS_OCM_DATA_ADDR@h	/* OCM location */
+	ori	r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
 	mtdcr	ocmdsarc, r3
 	addis	r4, 0, 0xC000		/* OCM data area enabled */
 	mtdcr	ocmdscntl, r4
@@ -1015,26 +1015,26 @@ _start:
 	/*----------------------------------------------------------------------- */
 	/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 	/*----------------------------------------------------------------------- */
-#ifdef CFG_INIT_DCACHE_CS
+#ifdef CONFIG_SYS_INIT_DCACHE_CS
 	li	r4, PBxAP
 	mtdcr	ebccfga, r4
-	lis	r4, CFG_INIT_DCACHE_PBxAR@h
-	ori	r4, r4, CFG_INIT_DCACHE_PBxAR@l
+	lis	r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
+	ori	r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
 	mtdcr	ebccfgd, r4
 
 	addi	r4, 0, PBxCR
 	mtdcr	ebccfga, r4
-	lis	r4, CFG_INIT_DCACHE_PBxCR@h
-	ori	r4, r4, CFG_INIT_DCACHE_PBxCR@l
+	lis	r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
+	ori	r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
 	mtdcr	ebccfgd, r4
 
 	/*
 	 * Enable the data cache for the 128MB storage access control region
-	 * at CFG_INIT_RAM_ADDR.
+	 * at CONFIG_SYS_INIT_RAM_ADDR.
 	 */
 	mfdccr	r4
-	oris	r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
-	ori	r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
+	oris	r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori	r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
 	mtdccr	r4
 
 	/*
@@ -1044,11 +1044,11 @@ _start:
 	 */
 	li	r0, 0
 
-	lis	r3, CFG_INIT_RAM_ADDR@h
-	ori	r3, r3, CFG_INIT_RAM_ADDR@l
+	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 
-	lis	r4, CFG_INIT_RAM_END@h
-	ori	r4, r4, CFG_INIT_RAM_END@l
+	lis	r4, CONFIG_SYS_INIT_RAM_END@h
+	ori	r4, r4, CONFIG_SYS_INIT_RAM_END@l
 
 	/*
 	 * Convert the size, in bytes, to the number of cache lines/blocks
@@ -1072,18 +1072,18 @@ _start:
 	 * Load the initial stack pointer and data area and convert the size,
 	 * in bytes, to the number of words to initialize to a known value.
 	 */
-	lis	r1, CFG_INIT_RAM_ADDR@h
-	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+	lis	r1, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 
-	lis	r4, (CFG_INIT_RAM_END >> 2)@h
-	ori	r4, r4, (CFG_INIT_RAM_END >> 2)@l
+	lis	r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
+	ori	r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
 	mtctr	r4
 
-	lis	r2, CFG_INIT_RAM_ADDR@h
-	ori	r2, r2, CFG_INIT_RAM_END@l
+	lis	r2, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r2, r2, CONFIG_SYS_INIT_RAM_END@l
 
-	lis	r4, CFG_INIT_RAM_PATTERN@h
-	ori	r4, r4, CFG_INIT_RAM_PATTERN@l
+	lis	r4, CONFIG_SYS_INIT_RAM_PATTERN@h
+	ori	r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
 
 ..stackloop:
 	stwu	r4, -4(r2)
@@ -1106,15 +1106,15 @@ _start:
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
 
-#elif defined(CFG_TEMP_STACK_OCM) && \
-	(defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
+#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
+	(defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
 	/*
 	 * Stack in OCM.
 	 */
 
 	/* Set up Stack at top of OCM */
-	lis	r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
-	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
+	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
+	ori	r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
 
 	/* Set up a zeroized stack frame so that backtrace works right */
 	li	r0, 0
@@ -1130,7 +1130,7 @@ _start:
 	ori	r0, r0, RESET_VECTOR@l
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
-#endif /* CFG_INIT_DCACHE_CS */
+#endif /* CONFIG_SYS_INIT_DCACHE_CS */
 
 #ifdef CONFIG_NAND_SPL
 	bl	nand_boot_common	/* will not return */
@@ -1341,7 +1341,7 @@ in32r:
  */
 	.globl	relocate_code
 relocate_code:
-#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS)
+#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
 	/*
 	 * We need to flush the initial global data (gd_t) before the dcache
 	 * will be invalidated.
@@ -1354,10 +1354,10 @@ relocate_code:
 
 	/* Flush initial global data range */
 	mr	r3, r4
-	addi	r4, r4, CFG_GBL_DATA_SIZE@l
+	addi	r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
 	bl	flush_dcache_range
 
-#if defined(CFG_INIT_DCACHE_CS)
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
 	/*
 	 * Undo the earlier data cache set-up for the primordial stack and
 	 * data area. First, invalidate the data cache and then disable data
@@ -1366,19 +1366,19 @@ relocate_code:
 	 */
 
 	/* Invalidate the primordial stack and data area in cache */
-	lis	r3, CFG_INIT_RAM_ADDR@h
-	ori	r3, r3, CFG_INIT_RAM_ADDR@l
+	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 
-	lis	r4, CFG_INIT_RAM_END@h
-	ori	r4, r4, CFG_INIT_RAM_END@l
+	lis	r4, CONFIG_SYS_INIT_RAM_END@h
+	ori	r4, r4, CONFIG_SYS_INIT_RAM_END@l
 	add	r4, r4, r3
 
 	bl	invalidate_dcache_range
 
 	/* Disable cacheability for the region */
 	mfdccr	r3
-	lis     r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
-	ori     r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
+	lis     r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
+	ori     r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
 	and     r3, r3, r4
 	mtdccr  r3
 
@@ -1394,15 +1394,15 @@ relocate_code:
 	lis	r3, PBxCR_VAL@h
 	ori	r3, r3, PBxCR_VAL@l
 	mtdcr	ebccfgd, r3
-#endif /* defined(CFG_INIT_DCACHE_CS) */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
 	/* Restore registers */
 	mr	r3, r9
 	mr	r4, r10
 	mr	r5, r11
-#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */
+#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/*
 	 * Unlock the previously locked d-cache
 	 */
@@ -1424,7 +1424,7 @@ relocate_code:
 	mtspr	dtv3,r6
 	msync
 	isync
-#endif /* CFG_INIT_RAM_DCACHE */
+#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@@ -1439,11 +1439,11 @@ relocate_code:
 	dccci	0,0			/* Invalidate data cache, now no longer our stack */
 	sync
 	isync
-#ifdef CFG_TLB_FOR_BOOT_FLASH
-	addi	r1,r0,CFG_TLB_FOR_BOOT_FLASH	/* Use defined TLB */
+#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
+	addi	r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH	/* Use defined TLB */
 #else
 	addi	r1,r0,0x0000		/* Default TLB entry is #0 */
-#endif /* CFG_TLB_FOR_BOOT_FLASH */
+#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
 	tlbre	r0,r1,0x0002		/* Read contents */
 	ori	r0,r0,0x0c00		/* Or in the inhibit, write through bit */
 	tlbwe	r0,r1,0x0002		/* Save it out */
@@ -1455,8 +1455,8 @@ relocate_code:
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
 	mr	r3,  r5				/* Destination Address	*/
-	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
-	ori	r4, r4, CFG_MONITOR_BASE@l
+	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
+	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
 	lwz	r5, GOT(__init_end)
 	sub	r5, r5, r4
 	li	r6, L1_CACHE_BYTES		/* Cache Line Size	*/
@@ -1464,7 +1464,7 @@ relocate_code:
 	/*
 	 * Fix GOT pointer:
 	 *
-	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
 	 *
 	 * Offset:
 	 */
@@ -1775,74 +1775,74 @@ ppc405ep_init:
 
 	lis	r3,GPIO0_OSRH@h		/* config GPIO output select */
 	ori	r3,r3,GPIO0_OSRH@l
-	lis	r4,CFG_GPIO0_OSRH@h
-	ori	r4,r4,CFG_GPIO0_OSRH@l
+	lis	r4,CONFIG_SYS_GPIO0_OSRH@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_OSRH@l
 	stw	r4,0(r3)
 	lis	r3,GPIO0_OSRL@h
 	ori	r3,r3,GPIO0_OSRL@l
-	lis	r4,CFG_GPIO0_OSRL@h
-	ori	r4,r4,CFG_GPIO0_OSRL@l
+	lis	r4,CONFIG_SYS_GPIO0_OSRL@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_OSRL@l
 	stw	r4,0(r3)
 
 	lis	r3,GPIO0_ISR1H@h	/* config GPIO input select */
 	ori	r3,r3,GPIO0_ISR1H@l
-	lis	r4,CFG_GPIO0_ISR1H@h
-	ori	r4,r4,CFG_GPIO0_ISR1H@l
+	lis	r4,CONFIG_SYS_GPIO0_ISR1H@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
 	stw	r4,0(r3)
 	lis	r3,GPIO0_ISR1L@h
 	ori	r3,r3,GPIO0_ISR1L@l
-	lis	r4,CFG_GPIO0_ISR1L@h
-	ori	r4,r4,CFG_GPIO0_ISR1L@l
+	lis	r4,CONFIG_SYS_GPIO0_ISR1L@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
 	stw	r4,0(r3)
 
 	lis	r3,GPIO0_TSRH@h		/* config GPIO three-state select */
 	ori	r3,r3,GPIO0_TSRH@l
-	lis	r4,CFG_GPIO0_TSRH@h
-	ori	r4,r4,CFG_GPIO0_TSRH@l
+	lis	r4,CONFIG_SYS_GPIO0_TSRH@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_TSRH@l
 	stw	r4,0(r3)
 	lis	r3,GPIO0_TSRL@h
 	ori	r3,r3,GPIO0_TSRL@l
-	lis	r4,CFG_GPIO0_TSRL@h
-	ori	r4,r4,CFG_GPIO0_TSRL@l
+	lis	r4,CONFIG_SYS_GPIO0_TSRL@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_TSRL@l
 	stw	r4,0(r3)
 
 	lis	r3,GPIO0_TCR@h		/* config GPIO driver output enables */
 	ori	r3,r3,GPIO0_TCR@l
-	lis	r4,CFG_GPIO0_TCR@h
-	ori	r4,r4,CFG_GPIO0_TCR@l
+	lis	r4,CONFIG_SYS_GPIO0_TCR@h
+	ori	r4,r4,CONFIG_SYS_GPIO0_TCR@l
 	stw	r4,0(r3)
 
 	li	r3,pb1ap		/* program EBC bank 1 for RTC access */
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB1AP@h
-	ori	r3,r3,CFG_EBC_PB1AP@l
+	lis	r3,CONFIG_SYS_EBC_PB1AP@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB1AP@l
 	mtdcr	ebccfgd,r3
 	li	r3,pb1cr
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB1CR@h
-	ori	r3,r3,CFG_EBC_PB1CR@l
+	lis	r3,CONFIG_SYS_EBC_PB1CR@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB1CR@l
 	mtdcr	ebccfgd,r3
 
 	li	r3,pb1ap		/* program EBC bank 1 for RTC access */
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB1AP@h
-	ori	r3,r3,CFG_EBC_PB1AP@l
+	lis	r3,CONFIG_SYS_EBC_PB1AP@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB1AP@l
 	mtdcr	ebccfgd,r3
 	li	r3,pb1cr
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB1CR@h
-	ori	r3,r3,CFG_EBC_PB1CR@l
+	lis	r3,CONFIG_SYS_EBC_PB1CR@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB1CR@l
 	mtdcr	ebccfgd,r3
 
 	li	r3,pb4ap		/* program EBC bank 4 for FPGA access */
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB4AP@h
-	ori	r3,r3,CFG_EBC_PB4AP@l
+	lis	r3,CONFIG_SYS_EBC_PB4AP@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB4AP@l
 	mtdcr	ebccfgd,r3
 	li	r3,pb4cr
 	mtdcr	ebccfga,r3
-	lis	r3,CFG_EBC_PB4CR@h
-	ori	r3,r3,CFG_EBC_PB4CR@l
+	lis	r3,CONFIG_SYS_EBC_PB4CR@h
+	ori	r3,r3,CONFIG_SYS_EBC_PB4CR@l
 	mtdcr	ebccfgd,r3
 #endif
 
@@ -2111,20 +2111,20 @@ nand_boot_common:
 	 * First initialize SDRAM. It has to be available *before* calling
 	 * nand_boot().
 	 */
-	lis	r3,CFG_SDRAM_BASE@h
-	ori	r3,r3,CFG_SDRAM_BASE@l
+	lis	r3,CONFIG_SYS_SDRAM_BASE@h
+	ori	r3,r3,CONFIG_SYS_SDRAM_BASE@l
 	bl	initdram
 
 	/*
 	 * Now copy the 4k SPL code into SDRAM and continue execution
 	 * from there.
 	 */
-	lis	r3,CFG_NAND_BOOT_SPL_DST@h
-	ori	r3,r3,CFG_NAND_BOOT_SPL_DST@l
-	lis	r4,CFG_NAND_BOOT_SPL_SRC@h
-	ori	r4,r4,CFG_NAND_BOOT_SPL_SRC@l
-	lis	r5,CFG_NAND_BOOT_SPL_SIZE@h
-	ori	r5,r5,CFG_NAND_BOOT_SPL_SIZE@l
+	lis	r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
+	ori	r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
+	lis	r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
+	ori	r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
+	lis	r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
+	ori	r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
 	bl	nand_boot_relocate
 
 	/*
diff --git a/cpu/ppc4xx/usb.c b/cpu/ppc4xx/usb.c
index cb8d5c7..592efe7 100644
--- a/cpu/ppc4xx/usb.c
+++ b/cpu/ppc4xx/usb.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 
 #ifdef CONFIG_4xx_DCACHE
 #include <asm/mmu.h>
@@ -63,4 +63,4 @@ int usb_cpu_init_fail(void)
 	return 0;
 }
 
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index bfa79ab..2607ed6 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -1600,9 +1600,9 @@ int usb_lowlevel_init(void)
 	gohci.sleeping = 0;
 	gohci.irq = -1;
 #if defined(CONFIG_440EP)
-	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
-#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
-	gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
+	gohci.regs = (struct ohci_regs *)(CONFIG_SYS_PERIPHERAL_BASE | 0x1000);
+#elif defined(CONFIG_440EPX) || defined(CONFIG_SYS_USB_HOST)
+	gohci.regs = (struct ohci_regs *)(CONFIG_SYS_USB_HOST);
 #endif
 
 	gohci.flags = 0;
diff --git a/cpu/ppc4xx/usbdev.h b/cpu/ppc4xx/usbdev.h
index 3446d98..ef6a2da 100644
--- a/cpu/ppc4xx/usbdev.h
+++ b/cpu/ppc4xx/usbdev.h
@@ -1,31 +1,31 @@
 #include <config.h>
 
 /*Common Registers*/
-#define USB2D0_INTRIN_16   (CFG_USB_DEVICE | 0x100)
-#define USB2D0_POWER_8     (CFG_USB_DEVICE | 0x102)
-#define USB2D0_FADDR_8     (CFG_USB_DEVICE | 0x103)
-#define USB2D0_INTRINE_16  (CFG_USB_DEVICE | 0x104)
-#define USB2D0_INTROUT_16  (CFG_USB_DEVICE | 0x106)
-#define USB2D0_INTRUSBE_8  (CFG_USB_DEVICE | 0x108)
-#define USB2D0_INTRUSB_8   (CFG_USB_DEVICE | 0x109)
-#define USB2D0_INTROUTE_16 (CFG_USB_DEVICE | 0x10a)
-#define USB2D0_TSTMODE_8   (CFG_USB_DEVICE | 0x10c)
-#define USB2D0_INDEX_8     (CFG_USB_DEVICE | 0x10d)
-#define USB2D0_FRAME_16    (CFG_USB_DEVICE | 0x10e)
+#define USB2D0_INTRIN_16   (CONFIG_SYS_USB_DEVICE | 0x100)
+#define USB2D0_POWER_8     (CONFIG_SYS_USB_DEVICE | 0x102)
+#define USB2D0_FADDR_8     (CONFIG_SYS_USB_DEVICE | 0x103)
+#define USB2D0_INTRINE_16  (CONFIG_SYS_USB_DEVICE | 0x104)
+#define USB2D0_INTROUT_16  (CONFIG_SYS_USB_DEVICE | 0x106)
+#define USB2D0_INTRUSBE_8  (CONFIG_SYS_USB_DEVICE | 0x108)
+#define USB2D0_INTRUSB_8   (CONFIG_SYS_USB_DEVICE | 0x109)
+#define USB2D0_INTROUTE_16 (CONFIG_SYS_USB_DEVICE | 0x10a)
+#define USB2D0_TSTMODE_8   (CONFIG_SYS_USB_DEVICE | 0x10c)
+#define USB2D0_INDEX_8     (CONFIG_SYS_USB_DEVICE | 0x10d)
+#define USB2D0_FRAME_16    (CONFIG_SYS_USB_DEVICE | 0x10e)
 
 /*Indexed Registers*/
-#define USB2D0_INCSR0_8    (CFG_USB_DEVICE | 0x110)
-#define USB2D0_INCSR_16    (CFG_USB_DEVICE | 0x110)
-#define USB2D0_INMAXP_16   (CFG_USB_DEVICE | 0x112)
-#define USB2D0_OUTCSR_16   (CFG_USB_DEVICE | 0x114)
-#define USB2D0_OUTMAXP_16  (CFG_USB_DEVICE | 0x116)
-#define USB2D0_OUTCOUNT0_8 (CFG_USB_DEVICE | 0x11a)
-#define USB2D0_OUTCOUNT_16 (CFG_USB_DEVICE | 0x11a)
+#define USB2D0_INCSR0_8    (CONFIG_SYS_USB_DEVICE | 0x110)
+#define USB2D0_INCSR_16    (CONFIG_SYS_USB_DEVICE | 0x110)
+#define USB2D0_INMAXP_16   (CONFIG_SYS_USB_DEVICE | 0x112)
+#define USB2D0_OUTCSR_16   (CONFIG_SYS_USB_DEVICE | 0x114)
+#define USB2D0_OUTMAXP_16  (CONFIG_SYS_USB_DEVICE | 0x116)
+#define USB2D0_OUTCOUNT0_8 (CONFIG_SYS_USB_DEVICE | 0x11a)
+#define USB2D0_OUTCOUNT_16 (CONFIG_SYS_USB_DEVICE | 0x11a)
 
 /*FIFOs*/
-#define USB2D0_FIFO_0 (CFG_USB_DEVICE | 0x120)
-#define USB2D0_FIFO_1 (CFG_USB_DEVICE | 0x124)
-#define USB2D0_FIFO_2 (CFG_USB_DEVICE | 0x128)
-#define USB2D0_FIFO_3 (CFG_USB_DEVICE | 0x12c)
+#define USB2D0_FIFO_0 (CONFIG_SYS_USB_DEVICE | 0x120)
+#define USB2D0_FIFO_1 (CONFIG_SYS_USB_DEVICE | 0x124)
+#define USB2D0_FIFO_2 (CONFIG_SYS_USB_DEVICE | 0x128)
+#define USB2D0_FIFO_3 (CONFIG_SYS_USB_DEVICE | 0x12c)
 
 void usb_dev_init(void);