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| author | Adam Graham <agraham@amcc.com> | 2008-10-06 10:16:13 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-10-08 11:36:23 +0200 |
| commit | f8a00dea841d5d75de1f8e8107e90ee1beeddf5f (patch) | |
| tree | 819dece576ce94a497c9c95dd5a1c917efd84980 /cpu/ppc4xx | |
| parent | 50a874b3b0272f32e3627732fab90b27fbd35066 (diff) | |
| download | u-boot-imx-f8a00dea841d5d75de1f8e8107e90ee1beeddf5f.zip u-boot-imx-f8a00dea841d5d75de1f8e8107e90ee1beeddf5f.tar.gz u-boot-imx-f8a00dea841d5d75de1f8e8107e90ee1beeddf5f.tar.bz2 | |
ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
| -rw-r--r-- | cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 83b9883..47ab39b 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -174,6 +174,23 @@ static inline void ecc_clear_status_reg(void) #endif } +/* + * Reset and relock memory DLL after SDRAM_CLKTR change + */ +static inline void relock_memory_DLL(void) +{ + u32 reg; + + mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE); + + do { + mfsdram(SDRAM_MCSTAT, reg); + } while (!(reg & SDRAM_MCSTAT_MIC_COMP)); + + mfsdram(SDRAM_MCOPT2, reg); + mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE); +} + static int ecc_check_status_reg(void) { u32 ecc_status; @@ -981,6 +998,8 @@ u32 DQS_autocalibration(void) mtsdram(SDRAM_CLKTR, clkp << 30); + relock_memory_DLL(); + putc('\b'); putc(slash[loopi++ % 8]); @@ -1170,6 +1189,8 @@ u32 DQS_autocalibration(void) mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30); + relock_memory_DLL(); + mfsdram(SDRAM_RQDC, rqdc_reg); rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); mtsdram(SDRAM_RQDC, rqdc_reg | |