Add support for multiple PHYs.

2 files changed, 47 insertions, 30 deletions

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index d3f1de4..2d2918e 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -142,7 +142,6 @@ static uint32_t mal_ier;
 struct eth_device *emac0_dev = NULL;
 #endif
 
-
 /*-----------------------------------------------------------------------------+
  * Prototypes and externals.
  *-----------------------------------------------------------------------------*/
@@ -154,6 +153,11 @@ static void mal_err (struct eth_device *dev, unsigned long isr,
 		     unsigned long mal_errr);
 static void emac_err (struct eth_device *dev, unsigned long isr);
 
+extern int phy_setup_aneg (char *devname, unsigned char addr);
+extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short *value);
+extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value);
 
 /*-----------------------------------------------------------------------------+
 | ppc_4xx_eth_halt
@@ -191,9 +195,6 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 	return;
 }
 
-extern int phy_setup_aneg (unsigned char addr);
-extern int miiphy_reset (unsigned char addr);
-
 #if defined (CONFIG_440GX)
 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 {
@@ -447,7 +448,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	 * otherwise, just check the speeds & feeds
 	 */
 	if (hw_p->first_init == 0) {
-		miiphy_reset (reg);
+		miiphy_reset (dev->name, reg);
 
 #if defined(CONFIG_440GX)
 #if defined(CONFIG_CIS8201_PHY)
@@ -457,9 +458,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		 */
 		if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
 #if defined(CONFIG_CIS8201_SHORT_ETCH)
-			miiphy_write (reg, 23, 0x1300);
+			miiphy_write (dev->name, reg, 23, 0x1300);
 #else
-			miiphy_write (reg, 23, 0x1000);
+			miiphy_write (dev->name, reg, 23, 0x1000);
 #endif
 			/*
 			 * Vitesse VSC8201/Cicada CIS8201 errata:
@@ -467,26 +468,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 			 * This work around (provided by Vitesse) changes
 			 * the default timer convergence from 8ms to 12ms
 			 */
-			miiphy_write (reg, 0x1f, 0x2a30);
-			miiphy_write (reg, 0x08, 0x0200);
-			miiphy_write (reg, 0x1f, 0x52b5);
-			miiphy_write (reg, 0x02, 0x0004);
-			miiphy_write (reg, 0x01, 0x0671);
-			miiphy_write (reg, 0x00, 0x8fae);
-			miiphy_write (reg, 0x1f, 0x2a30);
-			miiphy_write (reg, 0x08, 0x0000);
-			miiphy_write (reg, 0x1f, 0x0000);
+			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+			miiphy_write (dev->name, reg, 0x08, 0x0200);
+			miiphy_write (dev->name, reg, 0x1f, 0x52b5);
+			miiphy_write (dev->name, reg, 0x02, 0x0004);
+			miiphy_write (dev->name, reg, 0x01, 0x0671);
+			miiphy_write (dev->name, reg, 0x00, 0x8fae);
+			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+			miiphy_write (dev->name, reg, 0x08, 0x0000);
+			miiphy_write (dev->name, reg, 0x1f, 0x0000);
 			/* end Vitesse/Cicada errata */
 		}
 #endif
 #endif
 		/* Start/Restart autonegotiation */
-		phy_setup_aneg (reg);
+		phy_setup_aneg (dev->name, reg);
 		udelay (1000);
 	}
 #endif /* defined(CONFIG_PHY_RESET) */
 
-	miiphy_read (reg, PHY_BMSR, &reg_short);
+	miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
 
 	/*
 	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
@@ -508,7 +509,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 				putc ('.');
 			}
 			udelay (1000);	/* 1 ms */
-			miiphy_read (reg, PHY_BMSR, &reg_short);
+			miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
 
 		}
 		puts (" done\n");
@@ -516,8 +517,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	}
 #endif /* #ifndef CONFIG_CS8952_PHY */
 
-	speed = miiphy_speed (reg);
-	duplex = miiphy_duplex (reg);
+	speed = miiphy_speed (dev->name, reg);
+	duplex = miiphy_duplex (dev->name, reg);
 
 	if (hw_p->print_speed) {
 		hw_p->print_speed = 0;
@@ -1470,6 +1471,10 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 #else
 		emac0_dev = dev;
 #endif
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+		miiphy_register (dev->name,
+				emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
 
 	}			/* end for each supported device */
 	return (1);
@@ -1505,6 +1510,16 @@ int eth_rx(void)
 {
 	return (ppc_4xx_eth_rx(emac0_dev));
 }
+
+int emac4xx_miiphy_initialize (bd_t * bis)
+{
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+	miiphy_register ("ppc_4xx_eth0",
+			emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
+
+	return 0;
+}
 #endif /* !defined(CONFIG_NET_MULTI) */
 
 #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index 24f9154..f319eb8 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -55,14 +55,14 @@
 /* Dump out to the screen PHY regs			   */
 /***********************************************************/
 
-void miiphy_dump (unsigned char addr)
+void miiphy_dump (char *devname, unsigned char addr)
 {
 	unsigned long i;
 	unsigned short data;
 
 
 	for (i = 0; i < 0x1A; i++) {
-		if (miiphy_read (addr, i, &data)) {
+		if (miiphy_read (devname, addr, i, &data)) {
 			printf ("read error for reg %lx\n", i);
 			return;
 		}
@@ -79,21 +79,21 @@ void miiphy_dump (unsigned char addr)
 /***********************************************************/
 /* (Re)start autonegotiation				   */
 /***********************************************************/
-int phy_setup_aneg (unsigned char addr)
+int phy_setup_aneg (char *devname, unsigned char addr)
 {
 	unsigned short ctl, adv;
 
 	/* Setup standard advertise */
-	miiphy_read (addr, PHY_ANAR, &adv);
+	miiphy_read (devname, addr, PHY_ANAR, &adv);
 	adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
 		PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
 		PHY_ANLPAR_10);
-	miiphy_write (addr, PHY_ANAR, adv);
+	miiphy_write (devname, addr, PHY_ANAR, adv);
 
 	/* Start/Restart aneg */
-	miiphy_read (addr, PHY_BMCR, &ctl);
+	miiphy_read (devname, addr, PHY_BMCR, &ctl);
 	ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-	miiphy_write (addr, PHY_BMCR, ctl);
+	miiphy_write (devname, addr, PHY_BMCR, ctl);
 
 	return 0;
 }
@@ -142,7 +142,8 @@ unsigned int miiphy_getemac_offset (void)
 }
 
 
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+int emac4xx_miiphy_read (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short *value)
 {
 	unsigned long sta_reg;	/* STA scratch area */
 	unsigned long i;
@@ -207,7 +208,8 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
 /* write a phy reg and return the value with a rc	    */
 /***********************************************************/
 
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+int emac4xx_miiphy_write (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value)
 {
 	unsigned long sta_reg;	/* STA scratch area */
 	unsigned long i;