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| author | Marian Balakowicz <m8@semihalf.com> | 2006-06-30 16:30:46 +0200 |
|---|---|---|
| committer | Marian Balakowicz <m8@semihalf.com> | 2006-06-30 16:30:46 +0200 |
| commit | 6c5879f380be38d85fef0d3aba3353358f4b2ff4 (patch) | |
| tree | 32b48cff57dafc910c7b0dfdd6c5b99109c21e46 /cpu/ppc4xx/vecnum.h | |
| parent | bb105f24cc90ec4c56ea13012acc3d763b2a2984 (diff) | |
| download | u-boot-imx-6c5879f380be38d85fef0d3aba3353358f4b2ff4.zip u-boot-imx-6c5879f380be38d85fef0d3aba3353358f4b2ff4.tar.gz u-boot-imx-6c5879f380be38d85fef0d3aba3353358f4b2ff4.tar.bz2 | |
Add support for AMCC 440SPe CPU based eval board (Yucca).
Diffstat (limited to 'cpu/ppc4xx/vecnum.h')
| -rw-r--r-- | cpu/ppc4xx/vecnum.h | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index cbfe41d..93cef02 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -31,7 +31,48 @@ #ifndef _VECNUMS_H_ #define _VECNUMS_H_ -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SPE) +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 7 /* PCI MSI level 0 */ +#define VECNUM_MSI1 8 /* PCI MSI level 0 */ +#define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 1 ) /* MAL SERR */ +#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ +#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ +#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ +#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ +#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ + +/* UIC 2 */ +#define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */ +#define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */ +#define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */ +#define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */ +#define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */ +#define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */ + +#elif defined(CONFIG_440SP) /* UIC 0 */ #define VECNUM_U0 0 /* UART0 */ |