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authorSandeep Paulraj <s-paulraj@ti.com>2009-08-10 13:27:56 -0400
committerScott Wood <scottwood@freescale.com>2009-08-26 15:37:03 -0500
commitf83b7f9e8a5d1334e24506ea5953dd871596ea8a (patch)
treeca8a545a60fa8fbc6f912ff6286ea1bd78c4b0a1 /cpu/ppc4xx/uic.c
parent36fab997d85d89ee7fd2c7fd6057fab786d556aa (diff)
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MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRST
This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'cpu/ppc4xx/uic.c')
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