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authorAnatolij Gustschin <agust@denx.de>2008-04-17 18:15:27 +0200
committerWolfgang Denk <wd@denx.de>2008-04-18 00:48:02 -0700
commitaccf7355767dc7f6b85d88bb1c75c9d95e84ba5b (patch)
treed57d97546f1c3c9db1ffdd19ff57522ee06e2218 /cpu/ppc4xx/tlb.c
parent43c509254fab375c49936498da944658117ed07c (diff)
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ppc4xx: Fix crash on sequoia with cache enabled
Currently U-Boot crashes on sequoia board in CPU POST if cache is enabled (CONFIG_4xx_DCACHE defined). The cache won't be disabled by change_tlb before CPU POST because there is an insufficient adress range check since CFG_MEM_TOP_HIDE was introduced. This patch tries to fix this problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'cpu/ppc4xx/tlb.c')
-rw-r--r--cpu/ppc4xx/tlb.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c
index 2bfcba1..f44822d 100644
--- a/cpu/ppc4xx/tlb.c
+++ b/cpu/ppc4xx/tlb.c
@@ -149,7 +149,9 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
/*
* Now check the end-address if it's in the range
*/
- if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) {
+ if (((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) ||
+ ((tlb_vaddr < (vaddr + size - 1)) &&
+ ((tlb_vaddr + tlb_size - 1) > (vaddr + size - 1)))) {
/*
* Found a TLB in the range.
* Change cache attribute in tlb2 word.