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| author | Rafal Jaworowski <raj@semihalf.com> | 2006-08-10 12:43:17 +0200 |
|---|---|---|
| committer | Rafal Jaworowski <raj@pollux.denx.de> | 2006-08-10 12:43:17 +0200 |
| commit | 692519b1edfd5803cd2a841921492889f46f0ce3 (patch) | |
| tree | 1a761268c5b203444769a19257a317d09ce396c4 /cpu/ppc4xx/start.S | |
| parent | edd6cf20e1be63f84e0f5af0280473cf31f0e86c (diff) | |
| download | u-boot-imx-692519b1edfd5803cd2a841921492889f46f0ce3.zip u-boot-imx-692519b1edfd5803cd2a841921492889f46f0ce3.tar.gz u-boot-imx-692519b1edfd5803cd2a841921492889f46f0ce3.tar.bz2 | |
Add support for PCI-Express on PPC440SPe (Yucca board).
Diffstat (limited to 'cpu/ppc4xx/start.S')
| -rw-r--r-- | cpu/ppc4xx/start.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 0a6f81d..6d6d75f 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -315,7 +315,23 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ /*----------------------------------------------------------------*/ /* TLB entry setup -- step thru tlbtab */ /*----------------------------------------------------------------*/ +#if defined(CONFIG_440SPE) + /*----------------------------------------------------------------*/ + /* We have different TLB tables for revA and rev B of 440SPe */ + /*----------------------------------------------------------------*/ + mfspr r1, PVR + lis r0,0x5342 + ori r0,r0,0x1891 + cmpw r7,r1,r0 + bne r7,..revA + bl tlbtabB + b ..goon +..revA: + bl tlbtabA +..goon: +#else bl tlbtab /* Get tlbtab pointer */ +#endif mr r5,r0 li r1,0x003f /* 64 TLB entries max */ mtctr r1 |