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| author | John Otken <john@softadvances.com> | 2007-07-26 17:49:11 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-07-26 17:49:11 +0200 |
| commit | d4024bb72dd81695ec099b2199eda0d27c623e62 (patch) | |
| tree | 401db21bb0c6665bb10ef70ece49a1479836483d /cpu/ppc4xx/start.S | |
| parent | 9f24a808f17fc0f37b7fb4805f734741335caecc (diff) | |
| download | u-boot-imx-d4024bb72dd81695ec099b2199eda0d27c623e62.zip u-boot-imx-d4024bb72dd81695ec099b2199eda0d27c623e62.tar.gz u-boot-imx-d4024bb72dd81695ec099b2199eda0d27c623e62.tar.bz2 | |
ppc4xx: Add support for AMCC 405EP Taihu board
Signed-off-by: John Otken <john@softadvances.com>
Diffstat (limited to 'cpu/ppc4xx/start.S')
| -rw-r--r-- | cpu/ppc4xx/start.S | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 8ecaaea..18d3445 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1869,6 +1869,11 @@ ppc405ep_init: ori r3,r3,CFG_EBC_PB4CR@l mtdcr ebccfgd,r3 #endif +#ifdef CONFIG_TAIHU + mfdcr r4, CPC0_BOOT + andi. r5, r4, CPC0_BOOT_SEP@l + bne strap_0 /* serial eeprom present */ +#endif #ifndef CFG_CPC0_PCI li r3,CPC0_PCI_HOST_CFG_EN @@ -1886,12 +1891,16 @@ ppc405ep_init: beq ..pci_cfg_set /* if not set, then bypass reg write*/ #endif ori r3,r3,CPC0_PCI_ARBIT_EN +#ifdef CONFIG_TAIHU + ori r3,r3,CPC0_PCI_SPE +#endif #else /* CFG_CPC0_PCI */ li r3,CFG_CPC0_PCI #endif /* CFG_CPC0_PCI */ ..pci_cfg_set: mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ +strap_0: /* !----------------------------------------------------------------------- ! Check to see if chip is in bypass mode. @@ -1947,11 +1956,35 @@ ppc405ep_init: ..no_pllset: #endif /* CONFIG_BUBINGA */ +#ifdef CONFIG_TAIHU + mfdcr r4, CPC0_BOOT + andi. r5, r4, CPC0_BOOT_SEP@l + bne strap_1 /* serial eeprom present */ + addis r5,0,CPLD_REG0_ADDR@h + ori r5,r5,CPLD_REG0_ADDR@l + andi. r5, r5, 0x10 + bne _pci_66mhz +#endif /* CONFIG_TAIHU */ + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ ori r3,r3,PLLMR0_DEFAULT@l /* */ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ ori r4,r4,PLLMR1_DEFAULT@l /* */ +#ifdef CONFIG_TAIHU + b 1f +_pci_66mhz: + addis r3,0,PLLMR0_DEFAULT_PCI66@h + ori r3,r3,PLLMR0_DEFAULT_PCI66@l + addis r4,0,PLLMR1_DEFAULT_PCI66@h + ori r4,r4,PLLMR1_DEFAULT_PCI66@l + b 1f +strap_1: + mfdcr r3, CPC0_PLLMR0 + mfdcr r4, CPC0_PLLMR1 +1: +#endif /* CONFIG_TAIHU */ + b pll_write /* Write the CPC0_PLLMR with new value */ pll_done: |