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| author | Stefan Roese <sr@denx.de> | 2007-03-01 21:11:36 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-01 21:11:36 +0100 |
| commit | ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35 (patch) | |
| tree | 1870475942be67d0516fc69095731bee3f925a99 /cpu/ppc4xx/start.S | |
| parent | 6c7cac8c4fce0ea2bf8e15ed8658d87974155b44 (diff) | |
| download | u-boot-imx-ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35.zip u-boot-imx-ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35.tar.gz u-boot-imx-ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35.tar.bz2 | |
[PATCH] Update AMCC Katmai 440SPe eval board support
This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.
Please note, that still some problems are left with some memory
configurations. See the driver for more details.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/start.S')
| -rw-r--r-- | cpu/ppc4xx/start.S | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a3db93f..cd2ccec 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1912,4 +1912,47 @@ pll_wait: TLBRE(3,3,0) blr function_epilog(mftlb1) + +/*----------------------------------------------------------------------------+ +| dcbz_area. ++----------------------------------------------------------------------------*/ + function_prolog(dcbz_area) + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 +..d_ra2:mtctr r5 +..d_ag2:dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag2 + sync + blr + function_epilog(dcbz_area) + +/*----------------------------------------------------------------------------+ +| dflush. Assume 32K at vector address is cachable. ++----------------------------------------------------------------------------*/ + function_prolog(dflush) + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 +..dflush_loop: + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 +..ag: dcbf r0,r3 + addi r3,r3,-32 + bdnz ..ag + sync + mtmsr r9 + blr + function_epilog(dflush) #endif /* CONFIG_440 */ |