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| author | Wolfgang Denk <wd@pollux.denx.de> | 2007-03-06 18:08:43 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-03-06 18:08:43 +0100 |
| commit | ad5bb451ade552c44bef9119d907929ebc2c126f (patch) | |
| tree | df979d3c6385a161cd6df6b6f903ed7eaad31948 /cpu/ppc4xx/start.S | |
| parent | a5284efd125967675b2e9c6ef7b95832268ad360 (diff) | |
| download | u-boot-imx-ad5bb451ade552c44bef9119d907929ebc2c126f.zip u-boot-imx-ad5bb451ade552c44bef9119d907929ebc2c126f.tar.gz u-boot-imx-ad5bb451ade552c44bef9119d907929ebc2c126f.tar.bz2 | |
Restructure POST directory to support of other CPUs, boards, etc.
Diffstat (limited to 'cpu/ppc4xx/start.S')
| -rw-r--r-- | cpu/ppc4xx/start.S | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 24b30df..6b2c170 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1916,43 +1916,43 @@ pll_wait: /*----------------------------------------------------------------------------+ | dcbz_area. +----------------------------------------------------------------------------*/ - function_prolog(dcbz_area) - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 + function_prolog(dcbz_area) + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 ..d_ra2:mtctr r5 ..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 - sync - blr - function_epilog(dcbz_area) + addi r3,r3,32 + bdnz ..d_ag2 + sync + blr + function_epilog(dcbz_area) /*----------------------------------------------------------------------------+ | dflush. Assume 32K at vector address is cachable. +----------------------------------------------------------------------------*/ - function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 + function_prolog(dflush) + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 ..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 ..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag - sync - mtmsr r9 - blr - function_epilog(dflush) + addi r3,r3,-32 + bdnz ..ag + sync + mtmsr r9 + blr + function_epilog(dflush) #endif /* CONFIG_440 */ |