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authorStefan Roese <sr@denx.de>2007-06-19 16:42:31 +0200
committerStefan Roese <sr@denx.de>2007-06-19 16:42:31 +0200
commitdf8a24cdd30151505cf57bbee5289e91bf53bd1b (patch)
treeff5305f90f000aead5a0cbf3a8e3501ea6102021 /cpu/ppc4xx/start.S
parent86ba99e34194394052d24c04dc40d1263d29a26f (diff)
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[ppc4xx] Fix problem with NAND booting on AMCC Acadia
The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/start.S')
-rw-r--r--cpu/ppc4xx/start.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index e135220..16df1e7 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -564,7 +564,7 @@ ProgramCheck:
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
STD_EXCEPTION(0xa00, APU, UnknownException)
-#endif
+#endif
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
#ifdef CONFIG_440
@@ -889,7 +889,7 @@ _start:
*/
lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
ori r3,r3,CFG_OCM_DATA_ADDR@l
- ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */
+ ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
mtdcr ocmplb3cr1,r3 /* Set PLB Access */
ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
mtdcr ocmplb3cr2,r3 /* Set PLB Access */
@@ -1623,7 +1623,7 @@ trap_init:
li r7, .L_APU - _start + _START_OFFSET
bl trap_reloc
-
+
li r7, .L_InstructionTLBError - _start + _START_OFFSET
bl trap_reloc