ppc4xx: Rework 4xx cache support

New cache handling functions added and all existing functions
moved from start.S into seperate cache.S.

Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 21 insertions, 123 deletions

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 81a15fe..f5a135f 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1220,111 +1220,6 @@ mck_return:
 #endif /* CONFIG_440 */
 
 
-/*
- * Cache functions.
- *
- * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
- * although for some cache-ralated calls stubs have to be provided to satisfy
- * symbols resolution.
- * Icache-related functions are used in POST framework.
- *
- */
-#ifdef CONFIG_440
-       .globl  dcache_disable
-       .globl  icache_disable
-       .globl  icache_enable
-dcache_disable:
-icache_disable:
-icache_enable:
-	blr
-
-	.globl	dcache_status
-	.globl	icache_status
-dcache_status:
-icache_status:
-	mr	r3,  0
-	blr
-#else
-flush_dcache:
-	addis	r9,r0,0x0002		/* set mask for EE and CE msr bits */
-	ori	r9,r9,0x8000
-	mfmsr	r12			/* save msr */
-	andc	r9,r12,r9
-	mtmsr	r9			/* disable EE and CE */
-	addi	r10,r0,0x0001		/* enable data cache for unused memory */
-	mfdccr	r9			/* region 0xF8000000-0xFFFFFFFF via */
-	or	r10,r10,r9		/* bit 31 in dccr */
-	mtdccr	r10
-
-	/* do loop for # of congruence classes. */
-	lis	r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS: for large cache sizes */
-	ori	r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
-	lis	r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
-	ori	r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
-	mtctr	r10
-	addi	r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
-	add	r11,r10,r11		/* add to get to other side of cache line */
-..flush_dcache_loop:
-	lwz	r3,0(r10)		/* least recently used side */
-	lwz	r3,0(r11)		/* the other side */
-	dccci	r0,r11			/* invalidate both sides */
-	addi	r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
-	addi	r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
-	bdnz	..flush_dcache_loop
-	sync				/* allow memory access to complete */
-	mtdccr	r9			/* restore dccr */
-	mtmsr	r12			/* restore msr */
-	blr
-
-	.globl	icache_enable
-icache_enable:
-	mflr	r8
-	bl	invalidate_icache
-	mtlr	r8
-	isync
-	addis	r3,r0, 0xc000	      /* set bit 0 */
-	mticcr	r3
-	blr
-
-	.globl	icache_disable
-icache_disable:
-	addis	r3,r0, 0x0000	      /* clear bit 0 */
-	mticcr	r3
-	isync
-	blr
-
-	.globl	icache_status
-icache_status:
-	mficcr	r3
-	srwi	r3, r3, 31	/* >>31 => select bit 0 */
-	blr
-
-	.globl	dcache_enable
-dcache_enable:
-	mflr	r8
-	bl	invalidate_dcache
-	mtlr	r8
-	isync
-	addis	r3,r0, 0x8000	      /* set bit 0 */
-	mtdccr	r3
-	blr
-
-	.globl	dcache_disable
-dcache_disable:
-	mflr	r8
-	bl	flush_dcache
-	mtlr	r8
-	addis	r3,r0, 0x0000	      /* clear bit 0 */
-	mtdccr	r3
-	blr
-
-	.globl	dcache_status
-dcache_status:
-	mfdccr	r3
-	srwi	r3, r3, 31	/* >>31 => select bit 0 */
-	blr
-#endif
-
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
@@ -1430,6 +1325,26 @@ ppcSync:
  */
 	.globl	relocate_code
 relocate_code:
+#ifdef CONFIG_4xx_DCACHE
+	/*
+	 * We need to flush the Init Data before the dcache will be
+	 * invalidated
+	 */
+
+	/* save regs */
+	mr	r9,r3
+	mr	r10,r4
+	mr	r11,r5
+
+	mr	r3,r4
+	addi	r4,r4,0x200	/* should be enough for init data */
+	bl	flush_dcache_range
+
+	/* restore regs */
+	mr	r3,r9
+	mr	r4,r10
+	mr	r5,r11
+#endif
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
@@ -1457,7 +1372,7 @@ relocate_code:
 	ori	r4, r4, CFG_MONITOR_BASE@l
 	lwz	r5, GOT(__init_end)
 	sub	r5, r5, r4
-	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
+	li	r6, L1_CACHE_BYTES		/* Cache Line Size	*/
 
 	/*
 	 * Fix GOT pointer:
@@ -1777,23 +1692,6 @@ in32:
 	lwz	3,0x0000(3)
 	blr
 
-invalidate_icache:
-	iccci	r0,r0			/* for 405, iccci invalidates the */
-	blr				/*   entire I cache */
-
-invalidate_dcache:
-	addi	r6,0,0x0000		/* clear GPR 6 */
-	/* Do loop for # of dcache congruence classes. */
-	lis	r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha	/* TBS for large sized cache */
-	ori	r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
-					/* NOTE: dccci invalidates both */
-	mtctr	r7			/* ways in the D cache */
-..dcloop:
-	dccci	0,r6			/* invalidate line */
-	addi	r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
-	bdnz	..dcloop
-	blr
-
 /**************************************************************************/
 /* PPC405EP specific stuff						  */
 /**************************************************************************/