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| author | Stefan Roese <sr@denx.de> | 2007-03-24 15:59:23 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-24 15:59:23 +0100 |
| commit | e50b791b3f8b696e32000bbaa6e2d1f098c4bc04 (patch) | |
| tree | 6a7953a8761f860be7f5ba8054d3582076bc10cc /cpu/ppc4xx/start.S | |
| parent | e6615ecf4eaf4dd52696934aed8f5c6474cfd286 (diff) | |
| parent | 0d974d5297349504a2ddfa09314be573b5df320a (diff) | |
| download | u-boot-imx-e50b791b3f8b696e32000bbaa6e2d1f098c4bc04.zip u-boot-imx-e50b791b3f8b696e32000bbaa6e2d1f098c4bc04.tar.gz u-boot-imx-e50b791b3f8b696e32000bbaa6e2d1f098c4bc04.tar.bz2 | |
Merge with /home/stefan/git/u-boot/acadia
Diffstat (limited to 'cpu/ppc4xx/start.S')
| -rw-r--r-- | cpu/ppc4xx/start.S | 51 |
1 files changed, 9 insertions, 42 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index d918b3e..3b1586c 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -2,6 +2,7 @@ * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> + * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering * * See file CREDITS for list of people who contributed to this * project. @@ -757,7 +758,6 @@ _start: #endif /* CONFIG_405EP */ #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) -/* test-only... (clean up later when NAND booting is supported) */ #if defined(CONFIG_405EZ) /******************************************************************** * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 @@ -786,41 +786,7 @@ _start: mtdcr ocmdsisdpc,r4 isync - -#if defined(CONFIG_NAND_SPL) - /* - * 405EZ can boot from NAND Flash. - * If we are booting the SPL (Pre-loader), copy code from - * the mapped 4K NAND Flash to the OCM - */ - li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 - mtctr r4 - lis r2,CFG_NAND_BOOT_SPL_SRC@h - ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l -spl_loop: - lwzu r4,4(r2) - stwu r4,4(r3) - bdnz spl_loop - - /* - * Jump to code in OCM Ram - */ - bl 00f -00: mflr r10 - lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h - ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l - sub r10,r10,r3 - addi r10,r10,28 - mtlr r10 - blr -start_ram: - sync - isync -#endif -#else -/* ...test-only */ +#else /* CONFIG_405EZ */ /******************************************************************** * Setup OCM - On Chip Memory *******************************************************************/ @@ -828,14 +794,15 @@ start_ram: lis r0, 0x7FFF ori r0, r0, 0xFFFF mfdcr r3, ocmiscntl /* get instr-side IRAM config */ - mfdcr r4, ocmdscntl /* get data-side IRAM config */ - and r3, r3, r0 /* disable data-side IRAM */ - and r4, r4, r0 /* disable data-side IRAM */ - mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ - mtdcr ocmdscntl, r4 /* set data-side IRAM config */ + mfdcr r4, ocmdscntl /* get data-side IRAM config */ + and r3, r3, r0 /* disable data-side IRAM */ + and r4, r4, r0 /* disable data-side IRAM */ + mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ + mtdcr ocmdscntl, r4 /* set data-side IRAM config */ isync - addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */ + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CFG_OCM_DATA_ADDR@l mtdcr ocmdsarc, r3 addis r4, 0, 0xC000 /* OCM data area enabled */ mtdcr ocmdscntl, r4 |