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authorRafal Jaworowski <raj@semihalf.com>2007-07-31 18:19:54 +0200
committerStefan Roese <sr@denx.de>2007-08-02 08:25:18 +0200
commitdec99558b9ea75a37940d07f41a3565a50b54ad1 (patch)
tree5ce95a3ed9f5ee894892e85774dcf8f945ef31e7 /cpu/ppc4xx/speed.c
parentd2f68006627eda6cb6c7f364bddf621dbfd2fc68 (diff)
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[ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A
This brings back separate settings for PCIe bus numbers depending on chip revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa commit. 440SPe rev. A does NOT work properly with the same settings as for the rev. B (no devices are seen on the bus during enumeration). Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
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