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| author | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-03-25 21:30:06 +0900 |
|---|---|---|
| committer | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-03-25 21:30:06 +0900 |
| commit | 2e0e5271aac917812a76c72030a2b2c6f1d3387d (patch) | |
| tree | d2f724aa31ea7d3696170910069b6168437c7b0f /cpu/ppc4xx/speed.c | |
| parent | 1898840797c7f50799377bd5b285a8a93a82c419 (diff) | |
| download | u-boot-imx-2e0e5271aac917812a76c72030a2b2c6f1d3387d.zip u-boot-imx-2e0e5271aac917812a76c72030a2b2c6f1d3387d.tar.gz u-boot-imx-2e0e5271aac917812a76c72030a2b2c6f1d3387d.tar.bz2 | |
[MIPS] Fix I-/D-cache initialization loops
Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I
again per a loop for I-cache initialization. But according to 'See MIPS
Run', we're encouraged to use three separate loops rather than combining
them *for both I- and D-cache*. This patch tries to fix this.
In accordance with fixing above, mips_init_[id]cache are separated from
mips_cache_reset(), and rewrite cache loops are completely rewritten with
useful macros.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu/ppc4xx/speed.c')
0 files changed, 0 insertions, 0 deletions