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authorStefan Roese <sr@denx.de>2006-07-28 18:34:58 +0200
committerStefan Roese <sr@denx.de>2006-07-28 18:34:58 +0200
commita2c95a72247990dee9a03b26b4dc9fc0182c97ed (patch)
treecabdaa860480f895cccc6600f3454a751329c13c /cpu/ppc4xx/spd_sdram.c
parentfc6c4a67ae94adac02da6257a0f5adc3bd48ebec (diff)
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PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on the PPC440 DDR controller. Please see doc/README.440-DDR-performance for details. Patch by Stefan Roese, 28 Jul 2006
Diffstat (limited to 'cpu/ppc4xx/spd_sdram.c')
-rw-r--r--cpu/ppc4xx/spd_sdram.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index c0a6933..c24456b 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -1007,9 +1007,9 @@ void program_cfg0(unsigned long* dimm_populated,
}
/*
- * program Page Management Unit
+ * program Page Management Unit (0 == enabled)
*/
- cfg0 |= SDRAM_CFG0_PMUD;
+ cfg0 &= ~SDRAM_CFG0_PMUD;
/*
* program Memory Controller Options 0