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authorStefan Roese <sr@denx.de>2005-08-04 17:09:16 +0200
committerStefan Roese <sr@denx.de>2005-08-04 17:09:16 +0200
commit17f50f22bc3f2d17258523f2ef3074e6ce1f7ffa (patch)
tree2c5d47cd55f487f0504458908d587e9bcd6963a6 /cpu/ppc4xx/spd_sdram.c
parent3e0bc4473add883fd68a49b7dab971191b943415 (diff)
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Add support for AMCC Bamboo PPC440EP eval board
Patch by Stefan Roese, 04 Aug 2005
Diffstat (limited to 'cpu/ppc4xx/spd_sdram.c')
-rw-r--r--cpu/ppc4xx/spd_sdram.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index 520107a..e2eab62 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -1590,7 +1590,6 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
unsigned long num_dimm_banks)
{
unsigned long dimm_num;
- unsigned long bxcr_num;
unsigned long bank_base_addr;
unsigned long bank_size_bytes;
unsigned long cr;
@@ -1601,6 +1600,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
unsigned char num_banks;
unsigned char bank_size_id;
+#ifndef CONFIG_BAMBOO
+ unsigned long bxcr_num;
/*
* Set the BxCR regs. First, wipe out the bank config registers.
@@ -1609,11 +1610,16 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
mtdcr(memcfgd, 0x00000000);
}
+#endif
/*
* reset the bank_base address
*/
+#ifndef CONFIG_BAMBOO
bank_base_addr = CFG_SDRAM_BASE;
+#else
+ bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
+#endif
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
@@ -1691,7 +1697,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
+-----------------------------------------------------------------*/
if (dimm_num == 0) {
for (i = 0; i < num_banks; i++) {
+#ifndef CONFIG_BAMBOO
mtdcr(memcfga, mem_b0cr + (i << 2));
+#else
+ mtdcr(memcfga, mem_b1cr + (i << 2));
+#endif
temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK |
@@ -1703,7 +1713,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
}
} else {
for (i = 0; i < num_banks; i++) {
+#ifndef CONFIG_BAMBOO
mtdcr(memcfga, mem_b2cr + (i << 2));
+#else
+ mtdcr(memcfga, mem_b3cr + (i << 2));
+#endif
temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK |