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authorStefan Roese <sr@denx.de>2006-07-28 18:34:58 +0200
committerStefan Roese <sr@denx.de>2006-07-28 18:34:58 +0200
commita2c95a72247990dee9a03b26b4dc9fc0182c97ed (patch)
treecabdaa860480f895cccc6600f3454a751329c13c /cpu/ppc4xx/sdram.c
parentfc6c4a67ae94adac02da6257a0f5adc3bd48ebec (diff)
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PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on the PPC440 DDR controller. Please see doc/README.440-DDR-performance for details. Patch by Stefan Roese, 28 Jul 2006
Diffstat (limited to 'cpu/ppc4xx/sdram.c')
-rw-r--r--cpu/ppc4xx/sdram.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index e31d59d..faeea5c 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -379,7 +379,7 @@ long int initdram(int board_type)
/*
* Enable the controller, then wait for DCEN to complete
*/
- mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {