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authorWilliam Juul <william.juul@datarespons.no>2007-10-31 13:53:06 +0100
committerScott Wood <scottwood@freescale.com>2008-08-12 11:31:15 -0500
commitcfa460adfdefcc30d104e1a9ee44994ee349bb7b (patch)
tree59400f96629aec9c968b0e3251628302824f5d35 /cpu/ppc4xx/ndfc.c
parentcd82919e6c8a73b363a26f34b734923844e52d1c (diff)
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Update MTD to that of Linux 2.6.22.1
A lot changed in the Linux MTD code, since it was last ported from Linux to U-Boot. This patch takes U-Boot NAND support to the level of Linux 2.6.22.1 and will enable support for very large NAND devices (4KB pages) and ease the compatibility between U-Boot and Linux filesystems. This patch is tested on two custom boards with PPC and ARM processors running YAFFS in U-Boot and Linux using gcc-4.1.2 cross compilers. MAKEALL ppc/arm has some issues: * DOC/OneNand/nand_spl is not building (I have not tried porting these parts, and since I do not have any HW and I am not familiar with this code/HW I think its best left to someone else.) Except for the issues mentioned above, I have ported all drivers necessary to run MAKEALL ppc/arm without errors and warnings. Many drivers were trivial to port, but some were not so trivial. The following drivers must be examined carefully and maybe rewritten to some degree: cpu/ppc4xx/ndfc.c cpu/arm926ejs/davinci/nand.c board/delta/nand.c board/zylonite/nand.c Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Stig Olsen <stig.olsen@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'cpu/ppc4xx/ndfc.c')
-rw-r--r--cpu/ppc4xx/ndfc.c57
1 files changed, 21 insertions, 36 deletions
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 5b2ae88..7818eb9 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -46,38 +46,22 @@
static u8 hwctl = 0;
-static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- switch (cmd) {
- case NAND_CTL_SETCLE:
- hwctl |= 0x1;
- break;
-
- case NAND_CTL_CLRCLE:
- hwctl &= ~0x1;
- break;
-
- case NAND_CTL_SETALE:
- hwctl |= 0x2;
- break;
-
- case NAND_CTL_CLRALE:
- hwctl &= ~0x2;
- break;
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE )
+ hwctl |= 0x1;
+ else
+ hwctl &= ~0x1;
+ if ( ctrl & NAND_ALE )
+ hwctl |= 0x2;
+ else
+ hwctl &= ~0x2;
}
-}
-
-static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
- struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
-
- if (hwctl & 0x1)
- out_8((u8 *)(base + NDFC_CMD), byte);
- else if (hwctl & 0x2)
- out_8((u8 *)(base + NDFC_ALE), byte);
- else
- out_8((u8 *)(base + NDFC_DATA), byte);
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
@@ -194,16 +178,17 @@ int board_nand_init(struct nand_chip *nand)
int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
- nand->hwcontrol = ndfc_hwcontrol;
+ nand->cmd_ctrl = ndfc_hwcontrol;
nand->read_byte = ndfc_read_byte;
nand->read_buf = ndfc_read_buf;
- nand->write_byte = ndfc_write_byte;
nand->dev_ready = ndfc_dev_ready;
- nand->eccmode = NAND_ECC_HW3_256;
- nand->enable_hwecc = ndfc_enable_hwecc;
- nand->calculate_ecc = ndfc_calculate_ecc;
- nand->correct_data = nand_correct_data;
+ nand->ecc.correct = nand_correct_data;
+ nand->ecc.hwctl = ndfc_enable_hwecc;
+ nand->ecc.calculate = ndfc_calculate_ecc;
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = 256;
+ nand->ecc.bytes = 3;
#ifndef CONFIG_NAND_SPL
nand->write_buf = ndfc_write_buf;