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author <m8@hekate.semihalf.com>2005-08-12 15:33:33 +0200
committer <m8@hekate.semihalf.com>2005-08-12 15:33:33 +0200
commit6df6d38d2d59ba2964e9ee33aa559707a6c1c4b7 (patch)
treebac8690410f0c5dba55f940d0bb403029459cdae /cpu/ppc4xx/miiphy_440.c
parent5a27f84855f3db8a6317389c034f8f507444185f (diff)
parentdafba16e6fc1837381c8e74c4891ad6965cf54ab (diff)
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Merge with pollux.denx.org:/home/git/u-boot/.git
Diffstat (limited to 'cpu/ppc4xx/miiphy_440.c')
-rw-r--r--cpu/ppc4xx/miiphy_440.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/cpu/ppc4xx/miiphy_440.c b/cpu/ppc4xx/miiphy_440.c
index bbe535a..6320fea 100644
--- a/cpu/ppc4xx/miiphy_440.c
+++ b/cpu/ppc4xx/miiphy_440.c
@@ -165,13 +165,13 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
}
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_READ;
#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
@@ -225,13 +225,13 @@ int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
sta_reg = 0;
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_WRITE;
#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */