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authorWolfgang Denk <wd@pollux.denx.de>2005-08-12 23:55:10 +0200
committerWolfgang Denk <wd@pollux.denx.de>2005-08-12 23:55:10 +0200
commit55d150d95dbd4612f229e1f503c3a6aa8ed08a96 (patch)
treee8b755c6b0c5d56c8d8777236baab8b1deb67451 /cpu/ppc4xx/miiphy_440.c
parent2191923072413972d8dbf3e1b2f8ce6762a85800 (diff)
parent90e4e7836596d8ae5cead41a776b2b95c84182c6 (diff)
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Merge with /home/wd/git/u-boot/master
Diffstat (limited to 'cpu/ppc4xx/miiphy_440.c')
-rw-r--r--cpu/ppc4xx/miiphy_440.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/cpu/ppc4xx/miiphy_440.c b/cpu/ppc4xx/miiphy_440.c
index bbe535a..6320fea 100644
--- a/cpu/ppc4xx/miiphy_440.c
+++ b/cpu/ppc4xx/miiphy_440.c
@@ -165,13 +165,13 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
}
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_READ;
#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
@@ -225,13 +225,13 @@ int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
sta_reg = 0;
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_WRITE;
#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */