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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-11-27 16:13:00 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2006-11-27 16:13:00 +0100 |
| commit | d3c5e8b2f5945d93de8f23b053e9dcd033983245 (patch) | |
| tree | 72c292c41bc0dfadd6f634fe03e697d8a4473487 /cpu/ppc4xx/miiphy.c | |
| parent | 98280e3d431db77d92219438b8840853bd7cb412 (diff) | |
| parent | a9398e018593782c5fa7d0741955fc1256b34c1e (diff) | |
| download | u-boot-imx-d3c5e8b2f5945d93de8f23b053e9dcd033983245.zip u-boot-imx-d3c5e8b2f5945d93de8f23b053e9dcd033983245.tar.gz u-boot-imx-d3c5e8b2f5945d93de8f23b053e9dcd033983245.tar.bz2 | |
Merge with /home/wd/git/u-boot/master
Diffstat (limited to 'cpu/ppc4xx/miiphy.c')
| -rw-r--r-- | cpu/ppc4xx/miiphy.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index aa580ed..6b98025 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -173,7 +173,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, } sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; #else @@ -183,7 +184,9 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; #endif sta_reg = sta_reg | (addr << 5); /* Phy address */ @@ -244,7 +247,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = 0; sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; #else @@ -254,7 +258,9 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ + !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ |